AMS

Technologies

ams manufactures high performance analog semiconductors that solve its customers’ most challenging problems with innovative solutions.

ams

EUROPRACTICE partners CMP and Fraunhofer provide access to the following ams technologies:

0.35µm CMOS C35B4C3

Technology characteristicsMet. layer(s): 4
Poly layer(s): 2, high resistive poly
Maximum die size: 2cm x 2cm
DLP Usable cells: about 300 digital cells
Available I/O: I/O cell library with digital pads is available 3.3V, 3V/5V, 5V with internal level shifters
Temp. range: -40° C. / +125° C
Supply voltage: 5V or 3.3V
Special featuresHigh performance analog/digital process
Application areaMixed signal analog digital, large digital designs, system on chip
Design Kit version4.10 ISR 15
Frontend Backend toolsCadence IC 6.1.6
Simulation toolsSpectre (Cadence), Eldo (Mentor Graphics), Hspice (Synopsys)
Verification toolsAssura (Cadence), Calibre (Mentor Graphics)
Parasitics extraction toolsQRC (Cadence)
Place route toolsEncounter Digital Implementation (Cadence)
LibrariesAnalog libraries:
- A_CELLS: Low Voltage Analog Standard Cells
- ESDLIB, PRIMLIB, PRIMLIBRF: Primitive Devices
- IOLIB_ANA: Analog I/O pads & Power Supply Pads
- IOLIBC_ANA: Core Limited Analog I/O pads & Power Supply Pads
- IOLIB_ANA_3B: 3-Bus Analog I/O pads & Power Supply Pads
- SPIRALS_4M, SPIRALSD_4M : Inductors
Digital libraries:
- CORELIB: 3.3V Digital Standard Cells
- CORELIB_V5: 5V Digital Standard Cells
- CORELIB_3B: Digital Standard Cells with 3 Busses (VDD, VSS, GND)
- CORELIBD: Dense 3.3V Digital Standard Cells
- IOLIB_4M: Digital Input/Output/Bidirectional buffers & Power Pads
- IOLIBC: Core Limited Digital Input/Output/Bidirectional buffers & Power Pads
- IOLIB_V5: Digital Input/Output/Bidirectional buffers & Power Pads; 5V Supply
- IOLIB_3B: 3-Bus Digital Input/Output/Bidirectional buffers & Power Pads
Turnaround timeTypical leadtime: 10-12 weeks from MPW run deadline to packaged parts

0.35µm CMOS Opto C35B4O1

Technology characteristicsThis 0.35 CMOS-Opto process is offered in each 0.35 CMOS run (C35B4C3).
This is a ARC (Anti Reflective Coating) option.
Anti-Reflective Coating (ARC) allows a higher photo-sensitivity than C35B4C3.
P-Epi wafers for lowering current leakage in the diode (lower dark current).
The C35B4O1 is with 4 layers metal available for prototyping and low volume production.
Met. layer(s): 4
Poly layer(s): 2
Maximum die size: 2cm x 2cm
DLP Usable cells: about 300 digital cells
Available I/O: I/O cell library with digital pads is available 3V, 3V/5V, 5V with internal level shifters
Temp. range: -40° C. / +125° C
Supply voltage: 5V or 3.3V
Special FeaturesHigh performance analog/digital process + anti-reflective coating for optical devices
Application areaProvides enhanced optical sensitivity for embedded photodiodes and high density CMOS camera products.
Design Kit version4.10 ISR 15
Frontend Backend toolsCadence IC 6.1.6
Simulation toolsSpectre (Cadence), Eldo (Mentor Graphics), Hspice (Synopsys)
Verification toolsAssura (Cadence), Calibre (Mentor Graphics)
Parasitics extraction toolsQRC (Cadence)
Place route toolsEncounter Digital Implementation (Cadence)
LibrariesAnalog libraries:
- A_CELLS: Low Voltage Analog Standard Cells
- ESDLIB, PRIMLIB, PRIMLIBRF: Primitive Devices
- IOLIB_ANA: Analog I/O pads & Power Supply Pads
- IOLIBC_ANA: Core Limited Analog I/O pads & Power Supply Pads
- IOLIB_ANA_3B: 3-Bus Analog I/O pads & Power Supply Pads
- SPIRALS_4M, SPIRALSD_4M : Inductors
Digital libraries:
- CORELIB: 3.3V Digital Standard Cells
- CORELIB_V5: 5V Digital Standard Cells
- CORELIB_3B: Digital Standard Cells with 3 Busses (VDD, VSS, GND)
- CORELIBD: Dense 3.3V Digital Standard Cells
- IOLIB_4M: Digital Input/Output/Bidirectional buffers & Power Pads
- IOLIBC: Core Limited Digital Input/Output/Bidirectional buffers & Power Pads
- IOLIB_V5: Digital Input/Output/Bidirectional buffers & Power Pads; 5V Supply
- IOLIB_3B: 3-Bus Digital Input/Output/Bidirectional buffers & Power Pads
Turnaround timeTypical leadtime: 10-12 weeks from MPW run deadline to packaged parts

0.35µm CMOS Opto BARC C35B4OA

Technology characteristicsThis 0.35 CMOS-Opto option is offered in each 0.35 CMOS run (C35B4C3), this is a BARC (Bottom Anti Reflective Coating) option.
Botton Anti-Reflective Coating (BARC) allows a higher sensitivity than ARC.
P-Epi wafers for lowering current leakage in the diode (lower dark current).
The C35B4OA is with 4 metal layers available for prototyping and low volume production.
Met. layer(s): 4 Poly layer(s): 2
Maximum die size: 2cm x 2cm
DLP Usable cells: about 300 digital cells
Available I/O: I/O cell library with digital pads is available 3V, 3V/5V, 5V with internal level shifters
Temp. range: -40° C. / +125° C
Supply voltage: 5V or 3.3V
Special FeaturesHigh performance analog/digital process + bottom anti-reflective coating for optical devices.
Application areaProvides enhanced optical sensitivity for embedded photodiodes and high density CMOS camera products.
Design Kit version4.10 ISR 15
Frontend Backend toolsCadence IC 6.1.6
Simulation toolsSpectre (Cadence), Eldo (Mentor Graphics), Hspice (Synopsys)
Verification toolsAssura (Cadence), Calibre (Mentor Graphics)
Parasitics extraction toolsQRC (Cadence)
Place route toolsEncounter Digital Implementation (Cadence)
LibrariesAnalog libraries:
- A_CELLS: Low Voltage Analog Standard Cells
- ESDLIB, PRIMLIB, PRIMLIBRF: Primitive Devices
- IOLIB_ANA: Analog I/O pads & Power Supply Pads
- IOLIBC_ANA: Core Limited Analog I/O pads & Power Supply Pads
- IOLIB_ANA_3B: 3-Bus Analog I/O pads & Power Supply Pads
- SPIRALS_4M, SPIRALSD_4M: Inductors
Digital libraries:
- CORELIB: 3.3V Digital Standard Cells
- CORELIB_V5: 5V Digital Standard Cells
- CORELIB_3B: Digital Standard Cells with 3 Busses (VDD, VSS, GND)
- CORELIBD: Dense 3.3V Digital Standard Cells
- IOLIB_4M: Digital Input/Output/Bidirectional buffers & Power Pads
- IOLIBC: Core Limited Digital Input/Output/Bidirectional buffers & Power Pads
- IOLIB_V5: Digital Input/Output/Bidirectional buffers & Power Pads; 5V Supply
- IOLIB_3B: 3-Bus Digital Input/Output/Bidirectional buffers & Power Pads
Turnaround timeTypical leadtime: 10-12 weeks from MPW run deadline to packaged parts

0.35µm BiCMOS SiGe S35D4M5

Technology characteristicsMet. layer(s): 4, thick metal
MIM capacitor Poly layer(s): 2, high resistive poly
Maximum die size: 2cm x 2cm
Usable cells: about 300 digital cells
Available I/O: I/O cell library with digital pads is available 3V, 3V/5V, 5V with internal level shifters
Temp. range: -40° C. / +125° C
Supply voltage: 5V or 3.3V
Special featuresHigh performance analog/RF/digital process
Application areaMixed signal analog/RF/digital, large digital designs, system on chip
Design Kit version4.10 ISR 15
Frontend Backend toolsCadence IC 6.1.6
Simulation toolsSpectre (Cadence), Eldo (Mentor Graphics), Hspice (Synopsys)
Verification toolsAssura (Cadence), Calibre (Mentor Graphics)
Parasitics extraction toolsQRC (Cadence)
Place route toolsEncounter Digital Implementation (EDI) (Cadence)
LibrariesAnalog libraries:
- A_CELLS: Low Voltage Analog Standard Cells
- ESDLIB, PRIMLIB, PRIMLIBRF: Primitive Devices
- IOLIB_ANA: Analog I/O pads & Power Supply Pads
- IOLIBC_ANA: Core Limited Analog I/O pads & Power Supply Pads
- IOLIB_ANA_3B: 3-Bus Analog I/O pads & Power Supply Pads
- RFPADS_4M, RFPADS_3B_4M: RF Pads
- SPIRALS_4M, SPIRALSD_4M: Inductors
Digital libraries:
- CORELIB: 3.3V Digital Standard Cells
- CORELIB_V5: 5V Digital Standard Cells
- CORELIB_3B: Digital Standard Cells with 3 Busses (VDD, VSS, GND)
- CORELIBD: Dense 3.3V Digital Standard Cells
- IOLIB_4M: Digital Input/Output/Bidirectional buffers & Power Pads
- IOLIBC: Core Limited Digital Input/Output/Bidirectional buffers & Power Pads
- IOLIB_V5: Digital Input/Output/Bidirectional buffers & Power Pads; 5V Supply
- IOLIB_3B: 3-Bus Digital Input/Output/Bidirectional buffers & Power Pads
Turnaround timeTypical leadtime: 16-18 weeks from MPW run deadline to packaged parts

0.35µm CMOS High Voltage H35B4D3

Technology characteristicsMet. layer(s): 4
Thick Metal 4
Poly layer(s): 2, high resistive poly
Maximum die size: 2cm x 2cm
Usable cells: about 300 digital cells
Available I/O: I/O cell library with digital pads is available 3V, 3V/5V, 5V with internal level shifters
Floating digital pads available with 3.3V
Temp. range: -40° C. / +125° C
Supply voltage: 3.3V, 5V, 20V, 50V, 120V (max gate voltage 5V, 20V)
Special featuresHigh performance analog/digital/HV process
Application areaMixed signal analog digital, HV designs, system on chip
Design Kit version4.10 ISR 15
Frontend Backend toolsCadence IC 6.1.6
Simulation toolsSpectre (Cadence), Eldo (Mentor Graphics), Hspice (Synopsys)
Verification toolsAssura (Cadence), Calibre (Mentor Graphics)
Parasitics extraction toolsQRC (Cadence)
Place route toolsEncounter Digital Implementation (Cadence)
LibrariesAnalog libraries:
- A_CELLS, A_CELLS_HV: Low Voltage and 3.3V floating library Analog Standard Cells
- ESDLIB, PRIMLIB: Primitive Devices
- IOLIB_ANA: Analog I/O pads & Power Supply Pads
- IOLIBC_ANA: Core Limited Analog I/O pads & Power Supply Pads
- IOLIB_ANA_3B: 3-Bus Analog I/O pads & Power Supply Pads
- IOLIB_ANA_HV_4M: 50V floating library (Analog I/O pads & Power Supply Pads)
- IOLIB_ANA_120V_4M: 120V floating library (Analog I/O pads & Power Supply Pads)
Digital libraries:
- CORELIB: 3.3V Digital Standard Cells
- CORELIB_V5: 5V Digital Standard Cells
- CORELIB_3B: Digital Standard Cells with 3 Busses (VDD, VSS, GND)
- CORELIB_HV: floating library Digital Standard Cells
- CORELIBD: Dense 3.3V Digital Standard Cells
- IOLIB_4M: Digital Input/Output/Bidirectional buffers & Power Pads
- IOLIBC: Core Limited Digital Input/Output/Bidirectional buffers & Power Pads
- IOLIB_V5: Digital Input/Output/Bidirectional buffers & Power Pads; 5V Supply
- IOLIB_3B: 3-Bus Digital Input/Output/Bidirectional buffers & Power Pads
- IOLIB_HV_4M: 50V floating library (Digital Input/Output/Bidirectional buffers & Power Pads)
- IOLIB_120V_4M: 120V floating library (Digital Input/Output/Bidirectional buffers & Power Pads)
Turnaround timeTypical leadtime: 10-12 weeks from MPW run deadline to packaged parts

0.35µm Wafer-level bumping

Technology characteristicsSolder bumping consists in manufacturing metal spheres acting as interconnections for flip-chip. Those spheres are composed of a Sn/Ag/Cu alloy (SAC). Before the sphere can be deposited, the deposition of an Under Bump Metalization (UBM) layer is required.
This option, available on ams 0.35 & 0.18 runs only, is operated at wafer-level within ams cleanroom after CMOS process. It allows the deposition of an array of solder balls at wafer-level, with an I/O pitch compatible with traditional printed circuit board (PCB) assembly processes. For mechanical reasons solder balls are usually evenly distributed over the whole chip surface and electrically connected to the IC‘s CMOS pads by means of a redistribution layer (RDL) included in the option.
Application areaSingle die flip-chip packaging
Design Kit versionOption supported by ams hitkit 4.10 ISR15, through an add-on

In addition, CMP offers EUROPRACTICE customers the ams technologies listed below:

0.35µm CMOS RF C35B4M3

Technology characteristicsSame as C35B4C3 with Thick Metal module instead of Metal 4 module and with MIM capacitor module
Poly layer(s): 2, high resistive poly
Maximum die size: 2cm x 2cm
Usable cells: about 300 digital cells
Available I/O: I/O cell library with digital pads is available 3V, 3V/5V, 5V with internal level shifters
Temp. range: -40° C. / +125° C
Supply voltage: 5V or 3.3V
Special featuresHigh performance analog/digital/RF process
Application areaMixed signal analog digital, large digital designs, system on chip, RF.
Design Kit version4.10 ISR 15
Frontend Backend toolsCadence IC 6.1.6
Simulation toolsSpectre (Cadence), Eldo (Mentor Graphics), Hspice (Synopsys)
Verification toolsAssura (Cadence), Calibre (Mentor Graphics)
Parasitics extraction toolsQRC (Cadence)
Place route toolsEncounter Digital Implementation (Cadence)
LibrariesAnalog libraries:
- A_CELLS: Low Voltage Analog Standard Cells
- ESDLIB, PRIMLIB, PRIMLIBRF: Primitive Devices
- IOLIB_ANA: Analog I/O pads & Power Supply Pads
- IOLIBC_ANA: Core Limited Analog I/O pads & Power Supply Pads
- IOLIB_ANA_3B: 3-Bus Analog I/O pads & Power Supply Pads
- SPIRALS_4M, SPIRALSD_4M, SPIRALS_4M_THICKMET4: Inductors
Digital libraries:
- CORELIB: 3.3V Digital Standard Cells
- CORELIB_V5: 5V Digital Standard Cells
- CORELIB_3B: Digital Standard Cells with 3 Busses (VDD, VSS, GND)
- CORELIBD: Dense 3.3V Digital Standard Cells
- IOLIB_4M: Digital Input/Output/Bidirectional buffers & Power Pads
- IOLIBC: Core Limited Digital Input/Output/Bidirectional buffers & Power Pads
- IOLIB_V5: Digital Input/Output/Bidirectional buffers & Power Pads; 5V Supply
- IOLIB_3B: 3-Bus Digital Input/Output/Bidirectional buffers & Power Pads
Turnaround timeTypical leadtime: 10-12 weeks from MPW run deadline to packaged parts

0.35µm C35B4E3

Technology characteristicsEmbedded Flash
Met. layer(s): 4 Poly layer(s): 2
Maximum die size: 2cm x 2cm
Usable cells: about 300 digital cells
Available I/O: I/O cell library with digital pads is available 3V, 3V/5V, 5V with internal level shifters
Temp. range: -40° C. / +125° C
Supply voltage: 5V or 3.3V
Special featuresHigh performance analog/digital process embedding Flash/EEPROM
Application areaThe process is fully compatible with C35B4C3 Mixed signal analog digital, large digital designs, system on chip
Design Kit version4.10 ISR 15
Frontend Backend toolsCadence IC 6.1.6
Simulation toolsSpectre (Cadence), Eldo (Mentor Graphics), Hspice (Synopsys)
Verification toolsAssura (Cadence), Calibre (Mentor Graphics)
Parasitics extraction toolsQRC (Cadence)
Place route toolsEncounter Digital Implementation (Cadence)
LibrariesAnalog libraries:
- A_CELLS: Low Voltage Analog Standard Cells
- ESDLIB, PRIMLIB, PRIMLIBRF: Primitive Devices
- IOLIB_ANA: Analog I/O pads & Power Supply Pads
- IOLIBC_ANA: Core Limited Analog I/O pads & Power Supply Pads
- IOLIB_ANA_3B: 3-Bus Analog I/O pads & Power Supply Pads
- SPIRALS_4M, SPIRALSD_4M: Inductors
Digital libraries:
- CORELIB: 3.3V Digital Standard Cells
- CORELIB_V5: 5V Digital Standard Cells
- CORELIB_3B: Digital Standard Cells with 3 Busses (VDD, VSS, GND)
- CORELIBD: Dense 3.3V Digital Standard Cells
- IOLIB_4M: Digital Input/Output/Bidirectional buffers & Power Pads
- IOLIBC: Core Limited Digital Input/Output/Bidirectional buffers & Power Pads
- IOLIB_V5: Digital Input/Output/Bidirectional buffers & Power Pads; 5V Supply
- IOLIB_3B: 3-Bus Digital Input/Output/Bidirectional buffers & Power Pads
Turnaround timeTypical leadtime: 10-12 weeks from MPW run deadline to packaged parts

0.35µm Active Silicon Interposer with UBM

Active interposer 8fe6b
Technology characteristicsCMP, in partnership with ams, offers a 2.5D integration solution through specific MPW runs for silicon interposer production, allowing side by side integration of heterogeneous dies with higher interconnection densities than organic substrates, thus promoting package footprint reduction, increased inter-die bandwidth and decreased power consumption.
This interposer offer is based on ams C35B4 metal stack (including 4 metal levels for routing), upon which a post-process is performed by an external subcontractor in order to produce a front-side Under Bump Metalization (or UBM) consisting of Ni/Pd/Au stack. For this active interposer offer, Active layers are available for CMOS integration, allowing the implementation of a wide range of functions to the interposer.
The resulting interposer is ready to support flip-chip dies and is compatible with CMP OPEN 3D micro-bumps post-process offer (with a 50 µm min pitch). The interposer includes Wire-bonding pads to allow its connection to a PCB (as chip on board) or a compatible package. Note that this interposer is compatible with OPEN 3D TSV backside post-process.
Access to this silicon interposer offer is based upon a formal DK request as well as administrative and partners approval through our web interface. Interposer run offer is available at any time.
Guaranteed minimum delivered pieces: 40
ams CMOS C35 standard backend: 4 metal layers.
Size limit for submitted design is 400 mm2.
For design < 150 mm2, further cost reduction may be applicable under condition.
Application areaActive Silicon Si-Interposer for 3D/2.5D integration
Design Kit versionams C35B4 4.10 ISR15
Librariesams C35B4 libraries
Turnaround time23 weeks

Passive Silicon Interposer with UBM

Passive interposer 129d3
Technology characteristicsCMP, in partnership with ams, offers a 2.5D integration solution through specific MPW runs for silicon interposer production, allowing side by side integration of heterogeneous dies with higher interconnection densities than organic substrates, thus promoting package footprint reduction, increased inter-die bandwidth and decreased power consumption.
This interposer offer is based on ams C35B4 metal stack (including 4 metal levels for routing), upon which a post-process is performed by an external subcontractor in order to produce a front-side Under Bump Metalization (or UBM) consisting of Ni/Pd/Au stack.
For this passive interposer offer, only the backend is processed (no active component available), for high density routing applications and passive component integration.
The resulting interposer is ready to support flip-chip dies and is compatible with CMP OPEN 3D micro-bumps post-process offer (with a 50 µm min pitch). The interposer includes Wire-bonding pads to allow its connection to a PCB (as chip on board) or a compatible package. Note that this interposer is compatible with OPEN 3D TSV backside post-process.
Access to this silicon interposer offer is based upon a formal DK request as well as administrative and partners approval through our web interface. Interposer run offer is available at any time.
Guaranteed minimum delivered pieces: 40
ams CMOS C35 standard backend: 4 metal layers.
Size limit for submitted design is 400 mm2.
For design < 150 mm2, further cost reduction may be applicable under condition.
Application areaPassive Silicon Si-Interposer for 3D/2.5D integration
Design Kit versionams C35B4 4.10 ISR15
Librariesams C35B4 libraries
Turnaround time23 weeks

MEMS Backside Bulk Micromachining

Technology characteristicsams 0.35µ processes
4LM + Post Process On-chip suspended membrane with piezoresistors.
Special Features0.35 µm CMOS post process from ams + TMAH (Tetra Methyl Ammonium Hydroxide) post process etching ; No additional mask for the MEMS post process
Design Kit versionams C35B4 4.10 ISR15
Librariesams C35B4 libraries
Turnaround timeTypical leadtime: 14-16 weeks from MPW run deadline to packaged parts

MEMS Frontside Bulk Micromachining

Technology characteristicsams 0.35µ processes
Process cross section
Thick Metal module instead of Metal 4 module and with MIM capacitor module
Poly layer(s): 2, high resistive poly
Maximum die size: 2cm x 2cm
DLP Usable cells: about 300 digital cells
Available I/O: I/O cell library with digital pads is available 3.3V, 3V/5V, 5V with internal level shifters
Temp. range: -40° C. / +125° C
Supply voltage: 5V or 3.3V
Die size: Minimum charge of 3 mm².
Special features0.35 µm CMOS post process from ams + TMAH (Tetra Methyl Ammonium Hydroxide) post process etching ; No additional mask for the MEMS post process
Application areaMEMS, micromechanics, MOEMS.
Design Kit versionams C35B4 4.10 ISR15
Librariesams C35B4 libraries
Turnaround timeTypical leadtime: 14-16 weeks from MPW run deadline to to packaged parts

The CMP website provides more technical specifications.

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