CEA-LETI

Technologies

Memory Advanced Demonstrator 200mm (MAD200)

The EUROPRACTCE partner CMP provides access to HCMOS9A ST Microelectronics technology coupled with CEA-LETI post-process OxRAM Non volatile memory.

Technology characteristicsIn order to address new emerging Non-volatile memory technologies and to develop an optimized memory stack that targets the client requests, CEA-LETI with CMP offer a so-called Memory Advanced Demonstrator (MAD) Multi-Project Wafer based on 130 nm 200mm base wafers with 4 copper metal lines.
This technology builds on top of HCMOS9A ST Microelectronics. The post-process at CEA-LETI allows integration of additional layers at wafer level for NVM deposition.
The memory module, that can consist of OxRAM technology, is fabricated in the BEOL before pad level. This versatile test vehicle offers the possibility to have on the same silicon test structures spanning from simple resistors (1R), resistors with its selector transistor (1T1R), memory arrays (1kb cuts to 1Mb array) up to complex IC designs allowed by the routing placed on the 4 metal levels. All such structures are essential for a deep analysis of the memory functionality: From bulk material (with its interfaces) screening, obtained by the 1R and 1T1R; passing through statistical analysis of extrinsic bits, obtained by memory arrays; up to first validation of complex functions obtained by specific designs. MAD offers also a benchmark opportunity between different technologies (PCM, MRAM, CBRAM, …) with the same test vehicle in order to extract benefits and drawback from each of them.
Application areaStorage Class memory, Embedded memory, Neuromorphic, Computing, Artificial Intelligence accelerator.
Design kits version10.9-10-Addon_NVM_H9A@2018.4.1
DK font-end/back-end toolsVirtuoso (Cadence) –> release aligned on ST PDK
DK simulation toolsEldo (Mentor Graphics) –> release aligned on ST PDK
Price & Fabrication scheduleCheck mycmp.fr for new prices
PackagingAll packages provided by CMP
LibraryAddon_NVM_LibCategory Device:OxRAM
Typical Turnaround timeTypical leadtime: 24 weeks from MPW run deadling to packaged parts delivery

200mm Si-Photonics CMOS Si310-PHMP2M

This MPW capability on 310nm SOI platform is offering the design of various best performance passive and high-speed active devices such as silicon electro-optic modulators and germanium photo-detectors and still coupled with thermal tuning capability as metal heaters. Two AlCu levels are available for more optimal routing which is also compatible for backend treatment as Under Bump Metallization.

Technology characteristics200mm SOI platform with 300nm Si and 800nm buried oxide
Multilevel patterning to define various silicon heights of 0, 65, 165 and 300nm
2 metal layers
Passive structures
- 1D & 2D Grating couplers
- Shallow, deep rib and strip waveguides & bends
Active structures
- Lateral Ge PIN photodiode
- MZ and RR Modulators
- Multimode interferometers
- TiTiN Metal heater
Application areaTelecom, DataCom, ComputerCom.
Design kits version2019.1
DK font-end/back-end toolsCadence IC 6.1.5, Phoenix Software, Mentor Graphics Pyxis 15.5.5
DK simulation toolsEldo
Price & Fabrication scheduleCheck mycmp.fr for new prices
PackagingAll packages provided by CMP
Typical Turnaround timeTypical leadtime: 32 weeks

OPEN 3D post-process for 3D integration

CMP, in partnership with CEA-LETI, offers a set of post-processes allowing various types of 3D assemblies. Those post-processes are operated at wafer-level and are carried out after standard MPW runs on a selected subset of technologies. The goal is to integrate 3D interconnections to chips processed through CMP, in order to enable flip-chip on organic or ceramic substrates as well as Die-to-Die or Die-to-Interposer assemblies.

 

Two types of post-processes are available, including different options:

  • Front-side: 3D interconnections (µ-Bumps or UBM).
  • Back-side: Wafer thinning, TSV (via-last) and RDL, 3D interconnections (Bumps).

 

Technology characteristics:

µBumps (Cu-pillar)Cu/SnAg ; ø25 µm ; 50 µm min pitch ; ~20 µm thickness
UBMTiNiAu ; 25 µm min width; 50 µm min pitch ; 1 µm thickness
TSV-LASTØ60 µm x 120 µm depth ; 120 µm min pitch
Backside RDLCu ; 20 µm min width ; 40 µm min pitch ; 4-8 µm Thickness

Accessibility conditions:

  • As a MPW OPEN3D Front‐side post process (μ‐Bumps or UBM)
  • As a MPW OPEN3D Back‐side post process (TSV, RDL and Bumps)
  • As a MPW OPEN3D Back‐side + Front‐side post process (μ‐Bumps or UBM + TSV, RDL and Bumps)

MPW OPEN 3D post processes are available for projects and wafers processed through CMP on the last CMP MPW run of the year for the following technologies:

amsC35B4M3
CEA-LETISilicon Photonics
STMicroelectronicsCMOS28FDSOI (frontside only), BiCMOS055, CMOS065, BiCMOS9MW

Those runs are subject to a certain minimum number of participants sharing the MPW.

MPW OPEN 3D post‐processes must be anticipated at an early stage as they require an additional NDA, the distribution of a specific DRM and an add‐on to the Design‐Kit. Additionaly, this must be indicated it in the reservation form.

  • As a dedicated OPEN3D post‐process

Dedicated OPEN3D post processes can be made available on any CMP MPW Run at any time of the year after a feasibility study. In this case, restrictions to specific geometrical parameters of the design structure are not imposed and can be chosen within a process window. Please contact CMP for more information/quotation.

 

Application area:
3D/2.5D integration

 

Design kit version:

CMP/LETI 3D add-on is required to design post-processed modules

 

Verification tools:

DRC calibre die-level; DRC calibre 3Dstack for assembly-level checks (at CMP only)

 

Libraries:
3D modules Library

 

Packaging:
OPEN 3D post processing is available upon request, please contact ajith-sivadasan.moreau@mycmp.fr for more information on packaging solutions.

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