STMicroelectronics

Technologies

ST Microelectronic

CMP offers EUROPRACTICE customers access to the following STMicroelectronics technologies.

28nm CMOS FD-SOI ULP, MS/mmW/RF

Several process steps and masking levels are removed from the 28nm bulk process. This compensates the extra cost of the SOI substrate wafers. FD-SOI has lower channel leakage current. Carriers are efficiently confined from source to drain: the buried oxide prevent these carriers to spread into bulk. The process comes with NMOS and PMOS devices including body-bias-voltage scaling from 0V to +2V that helps decreases minimum circuit operating voltage. Standard-cells libraries are characterized over a range of voltages from 300mV to 1.2V.

Transistors can be ideally controlled through independent bias voltages. These body bias techniques allow dynamically modulating the transistor threshold voltage. Dynamic voltage and frequency scaling (DVFS) techniques can be applied more efficiently than alternative processes, therefore achieving high performance at conventional voltages.

Technology characteristicsCMOS gate length: 28nm drawn poly length
Triple well Fully Depleted SOI devices, with ultrathin BOX and Ground Plane
Body biasing Dual Vt MOS transistors (LVT, RVT)
Dual gate oxide (1.0V for core and 1.8V for IO)
Temperature range: -40°C to 175°C
Dual-damascene copper for interconnect, low-k dielectric
8 metal layers (8ML) for interconnect, 2 thick Cu top metal (0.880 micron)
Low k inter-level dielectric
Fringe MoM capacitors
Inductors
Analog / RF capabilities
Various power supplies supported: 1.8V, 1.0V
Standard cell libraries (more than 3Mgates/mm2)
Embedded memory (Single port RAM / ROM / Dual Port RAM).
Application areaLow power and high performance applications.
Design kits version1.0.a
DK font-end/back-end toolsCadence IC 6.1.7
DK simulation toolsSpectre (Cadence), Eldo (Mentor Graphics), Hspice (Synopsys), ADS Momentum (Keysight), GoldenGate (Keysight)
Price & Fabrication scheduleCheck mycmp.fr for new prices
PackagingAll packages provided by CMP
Typical Turnaround timeTypical leadtime: 24-32 weeks from MPW run deadline to packaged parts

55nm BiCMOS SiGe MS/mmW/RF

The BiCMOS055 technology of STMicroelectronics is well adapted for applications that require RF performance for analog part and high performance in digital part..

 

Bipolar SiGe transistors offer gain and high speed performances for analog devices:

  • Ft = 320GHz, fmax = 370GHz

CMOS 55nm transistors enable high speed and high density for digital devices:

  • 700 kgates/mm² for high speed gates
  • 970 kgates/mm² for high density gates
Technology characteristicsCMOS Gate length: 55nm drawn poly length
Deep Nwell and Deep Trench Isolation Triple Vt MOS transistors (LVT, RVT and SVT)
Low Power and General Purpose MOS transistors
Dual gate oxide (1.0V for core and 2.5V for IO)
Dedicated process flavors for high performance and for low power
Bipolar SiGe-C NPN transistors: High Speed NPN with Ft=320GHz
Medium Voltage NPN with Ft=180GHz, and High Voltage NPN
Temperature range: -40°C to 175°C
Dual-damascene copper for interconnect, low-k dielectric 8 Cu metal layers for interconnect
Ultra-thick Cu top metal (3.0 micron)
Low k inter-level dielectric
MiM capacitors & Fringe
MoM capacitors
Thin Film Resistors (RFR)
Millimiter-wave inductors
Analog / RF capabilities
Various power supplies supported: 2.5V, 1.2V, 1V
Standard cell libraries (more than 700kgates/mm² for high speed gates, more than 970kgates/mm² for high density gates)
Embedded memory (Single port RAM / ROM / Dual Port RAM).
Application areaOptical, Wireless and high performance analogue applications.
Design kits version2.8.a
DK font-end/back-end toolsCadence IC 6.1.7
DK simulation toolsSpectre (Cadence), Hspice (Synopsys), GoldenGate (Keysight)
Price & Fabrication scheduleCheck mycmp.fr for new prices
PackagingAll packages provided by CMP
Typical Turnaround timeTypical leadtime: 28-36 weeks from MPW run deadline to packaged parts

65nm CMOS MS/RF, LP/GP

The CMOS65LPGP technology has been introduced as general purpose and low power process to address 1.0V and 1.2V applications with 1.2V, 1.8V, 2.5V and 3.3V capable I/Os.

 

The design kit has a large bench of fully characterized devices. The RF kit includes inductors, varactors and MiM capacitors.

Technology characteristicsCMOS gate length: 65nm drawn poly length
Deep Nwell and Deep Trench Isolation
Triple Vt MOS transistors (LVT, RVT and SVT)
Low Power and General Purpose MOS transistors
Dual gate oxide (1.0V for core and 2.5V for IO)
Dedicated process flavors for high performance and for low power
Temperature range: -40°C to 175°C
Dual-damascene copper for interconnect, low-k dielectric 7 Cu metal layers for interconnect Low k inter-level dielectric
MiM capacitors & Fringe MoM capacitors
Inductors Analog / RF capabilities
Various power supplies supported: 2.5V, 1.2V, 1V
Standard cell libraries (more than 800kgates/mm2)
Embedded memory (Single port RAM / ROM / Dual Port RAM).
Application areaGeneral purpose, Analogue and RF capabilities.
Design kits version5.8
DK font-end/back-end toolsCadence IC 6.1.6
DK simulation toolsSpectre (Cadence), Eldo (Mentor Graphics), Hspice (Synopsys), ADS Momentum (Keysight), GoldenGate (Keysight)
Price & Fabrication scheduleCheck mycmp.fr for new prices
PackagingAll packages provided by CMP
Typical Turnaround timeTypical leadtime: 22-26 weeks from MPW run deadline to packaged parts

130nm HCMOS9GP

The HCMOS9GP technology is the main process for the 130 nm node. It has been introduced as a general‐purpose process to address 1.2V applications with 1.8V or 2.5V capable I/O’s.

The Design Kit provides a large bench of fully characterized devices, with standard Core cells and IO cells.

 

The design kit is provided with fully characterized devices:

  • General purpose NMOS and PMOS
  • Unsilicided P+ Poly resistors
  • Junction diode
  • N+Poly and P+Poly capacitors
  • Interdigited Metal Fringe capacitor (MOM).
Technology characteristicsCMOS gate length: 130nm drawn poly length
Deep Nwell and Deep Trench Isolation
Power supply 1.2V
Double Vt transistor offering (Low Leakage , High Speed)
Threshold voltages (for 2 families above): VTN = 450/340mV, VTP = 395/300mV
Isat (for 2 families above): TN @ 1.2V: 535/670uA/mic TP @ 1.2V: 240/310uA/mic
Dual gate oxide (1.2V for core and 2.5V for IO)
Temperature range: -40°C to 175°C 6 Cu metal layers for interconnect
Low k inter-level dielectric
MIM capacitors
Standard cell libraries (more than 180kgates/mm2)
Embedded memory (Single port RAM / ROM / Dual Port RAM).
Application areaGeneral purpose analogue/digital.
Design kits version9.2
DK font-end/back-end toolsCadence IC 5.1.41_USR6
DK simulation toolsSpectre (Cadence), Eldo (Mentor Graphics), Hspice (Synopsys)
Price & Fabrication scheduleCheck mycmp.fr for new prices
PackagingAll packages provided by CMP
Typical Turnaround timeTypical leadtime: 16-18 weeks from MPW run deadline to packaged parts

130nm BiCMOS9MW SiGe MS/RF

The BiCMOS9MW technology was defined by using the 130 nm HCMOS9 as base process and adds additional levels, in front‐end and back‐end. It has been introduced to address millimeterwave applications (Frequencies up to 77 GHz), wireless communication (around 60GHz for WLAN) and optical communications systems.

Technology characteristicsCMOS Gate length: 130nm drawn, 130nm effective
Deep Nwell and Deep Trench Isolation
Double Vt transistor offering (Low Leakage , High Speed)
Dual gate oxide (1.2V for core and 2.5V for IO)
Threshold voltages (for 2 families above): VTN = 450/340mV, VTP = 395/300mV
Isat (for 2 families above): TN @ 1.2V: 535/670uA/mic TP @ 1.2V: 240/310uA/mic
Bipolar SiGe transistors: High Speed NPN Medium VoltageNPN
Typical beta (for 2 families above): 1000/1000
Typical Ft (for 2 families above): 230/150GHz
Power supply 1.2V
Temperature range: -40°C to 175°C 6 Cu metal layers
Low k inter-level dielectric
MIM capacitors
Standard cell libraries (more than 180kgates/mm2)
Embedded memory (Single port RAM / ROM / dual port RAM).
Application areaRF applications and millimetre-waver application, WLAN, Optical communications.
Design kits version2.9.b
DK font-end/back-end toolsCadence IC 6.1.6
DK simulation toolsSpectre (Cadence), Eldo (Mentor Graphics), Hspice (Synopsys), ADS GoldenGate (Keysight)
Price & Fabrication scheduleCheck mycmp.fr for new prices
PackagingAll packages provided by CMP
Typical Turnaround timeTypical leadtime: 16-18 weeks from MPW run deadline to packaged parts

130nm HCMOS9‐SOI FEM

This technology is intended to serve at best RF ultra low cost applications.

 

H9‐SOI‐FEM is built on the same solid basis of the previous standard H9SOI technology and shares with it the robustness, the capability to address all FEM (stand for Front End Module) applications (RF Switches, PA, LNA) and the expertise in RF SOI process.

In addition, H9‐SOI‐FEM technology includes several improvements such as cost‐driven application, performance improvement and a better manufacturing capacity.

Technology characteristicsCMOS gate length: 130nm
SOI wafers with high resistive substrate 2.5V
Body Contacted CMOS
Floating Body CMOS 5.0V NLDMOS
PLDMOS 1.2V High Speed 130nm
CMOSmeta
Temperature range: -40°C to 175°C
4 metal layers for interconnect
Ultra-thick Cu top metal (4.0 micron)
High Linearity
MIM capacitor
Standard cell libraries.
Application areaRadio receiver/transceiver.
Design kits version14.1
DK font-end/back-end toolsCadence IC 6.1.6 Cadence IC 5.1.41_USR6
DK simulation toolsSpectre (Cadence), Eldo (Mentor Graphics),ADS GoldenGate (Keysight)
Price & Fabrication scheduleCheck mycmp.fr for new prices
PackagingAll packages provided by CMP
Typical Turnaround timeTypical leadtime: 16-18 weeks from MPW run deadline to packaged parts

130nm HCMOS9A LP/HV

This STMicroelectronics technology on the 130nm node, based on the HCMOS9GP DRM, targets the mixed digital analog design with energy management features.

Technology characteristicsCMOS gate length: 130nm drawnpoly length
Deep Nwell and Deep Trench Isolation
Vt transistor offering (Low Power, Analog)
Threshold voltages (for 2 families above): VTN = 700/697mV, VTP = 590/626mV
Isat (for 2 families above): TN: 280/658uA/um - TP: 104/333uA/um
Bipolar NPN transistors
Typical beta: 90 Ft Max @ Vbc=0: 2,4GHz
2 specific implant levels: NDRIFT & PDRIFT MIM 5fF/µm2
Double gate oxide for analog features
Temperature range: -40°C to 175°C
4 metal layers in standard Fluorinated SiO2
Inter Metal dielectrics
Power supply: 1. 2V for Digital, 4.6V for Analog application multiple
Standard cell libraries.
Application areaEnergy harvesting applications, Automous systems.
Design kits version10.9
DK font-end/back-end toolsCadence IC 6.1.6
DK simulation toolsSpectre (Cadence), Eldo (Mentor Graphics), Hspice (Synopsys)
Price & Fabrication scheduleCheck mycmp.fr for new prices
PackagingAll packages provided by CMP
Typical Turnaround timeTypical leadtime: 16-18 weeks from MPW run deadline to packaged parts

The design kit is provided with fully characterized devices:

HV MOS

  • N+ Poly/ 8.5 nm
  • N&P 8.5 nm Gate Oxide 20 V Drift MOS ‐ Extra masks : NDRIFT & PDRIFT
  • N&P 8.5nm Gate oxide 10V Drift MOS

Bipolar Transistors

  • NPN Bipolar N+/ Pdrift/ NISO ‐ Extra mask : PDRIFT
  • PNP

Capacitor

  • N+ Poly/ 8.5 nm Gate Oxide/ Nwell GO2
  • MOM Capacitor
  • Plate capacitor

MIM5 Capacitor.

0.16µm BCD8sP HV Bipolar-CMOS-DMOS

ST Microelectronics « Smart Power » BCD8sP technology combines high power transistors with low power digital and analog devices on a single chip. This technology is dedicated to power management systems, power supplies, motor drivers, amplifiers etc.

Technology characteristicsTemperature range: -40°C to +175°C 0.16µm
Bipolar-CMOS-DMOS
4 metal layers (2 top metal options : Al or CuRDL)
Baseline 1.8V
CMOS Power devices: 5V / 10V / 18V / 27V / 42V / 60V
Dual gate oxide process: 1.8V CMOS, 5V CMOS & Power Devices
Optional DTI for lateral isolation
Application areaHard disk drivers, DC-DC converters, Power management.
Design kits version2.4
DK font-end/back-end toolsCadence IC 6.1.6
DK simulation toolsSpectre (Cadence), Eldo (Mentor Graphics)
Price & Fabrication scheduleCheck mycmp.fr for new prices
PackagingAll packages provided by CMP
Typical Turnaround timeTypical leadtime: 18-24 weeks from MPW run deadline to packaged parts

0.16µm BCD8s-SOI HV Bipolar-CMOS-DMOS

ST Microelectronics « Smart Power » BCD8s-SOI technology is dedicated to high voltage applications on SOI substrates. This technology is convenient and even mandatory in case of MEMS & micro-mirror driver, consumer and automotive audio amplifiers, automotive sensor interface, 3D Ultrasound etc.

Technology characteristicsTemperature range: -40°C to +175°C 0.16µm
Bipolar-CMOS-DMOS 4 Metal Levels with last Al Thick Power metal
Baseline 3.3V CMOS
Medium Voltage Module: 6V / 20V / 40V NMOS and PMOS
High Voltage Module: 70V / 100V / 140V / 200V NMOS and PMOS Optional 2nd gate oxide for 1.8V
CMOS Dielectric Isolation on SOI
Available memory: OTP
Application area
Design kits version2.1
DK font-end/back-end toolsCadence IC 6.1.7
DK simulation toolsSpectre (Cadence), Eldo (Mentor Graphics)
Price & Fabrication scheduleCheck mycmp.fr for new prices
PackagingAll packages provided by CMP
Typical Turnaround timeTypical leadtime: 18-24 weeks from MPW run deadline to packaged parts

Copper-pillar Interconnections

Copper pillars are manufactured at wafer-level by STMicroelectronics. This interconnection is composed of an Under Bump Mettalization (UBM), upon which a pillar of copper is grown, a capping of Sn/Ag allows the die to be assembled on a substrate by reflow process. The dimensions of this copper pillar are approximately 62 µm in diameter for 65 µm in height, thus allowing a fine pitch (down to 90 µm).

 

Accessibility conditions:

  • Copper pillar option is available on CMOS28FDSOI, BiCMOS055, CMOS065 MPW and dedicated runs as options.
  • FC44S pad class must be used in the design to be compatible with this option.