TSMC

Technologies

TSMC

EUROPRACTICE customers can access the following TSMC technologies.

0.18µm CMOS High Voltage BCD Gen II

The 0.18 HV technololgy is based on the 1.8V/5V MS technology and adds 5V, 6V, 7V, 8V, 12V, 16V, 20V, 24V, 29V, 36V, 45V, 55V, 65V and 70V devices, aiming for high-voltage power management and automotive applications.

Technology characteristicsShrink technology: NO
Pore voltage1.8V
I/O voltage 5V
Shallow Trench Isolation (STI)
Wells: Retrograde four well on -100- P- substrate wafer.
Four LV wells, two HV wells and N+ Buried Layer (NBL)
Substrate resistivity 8~12 ohm.cm on -100- P- substrate
Standard Vt
Temperature range -40C to 150C
# of metals: 3 to 6
Interconnect material: AlCu
Interconnect dielectric: FSG
Top metal: 8KA, 15KA, 30KA or 40KA
CMP on STI, contact, via and inter-metal dielectric layers
OTP / MTP
MoM
MiM: 1fF/µm2 or 2fF/µm2, mutual exclusive
Passivation: single
Wafer size8 inch
Deliverables# of dies (no wafer!): 40 dies / wafer
Design toolsPDK: Cadence CDBA and OA
Simulation toolsHSPICE, Eldo, Spectre
Verification tools DRCCadence, Mentor Graphics
Verification tools LVSCadence, Mentor Graphics
Parasitic extraction toolsCadence, Synopsys
P&R toolsCadence, Synopsys
Foundry IP10-track core cell library, with 5V I/O devices, SVt
1.8V/5V linear universal standard I/O
5V/5V linear universal standard I/O
SRAM compilers by ARM, Dolphin Integration, Synopsys
MPW block sizeMin. 25 mm2, flexible aspect ratio
Mini@sic characteristicsSupported
Block size: 2550µm x 25000µm
5V
Metal scheme: 1P6M_4X1U with 30KA (UTM) topmetal
Mimcap: 2 fF between M5 & M6
Third party / at Foundry

0.18µm CMOS Logic or MS/RF, General Purpose 1.8V/3.3V

TSMC 0.18 µm technology with 6 metal layers. Highly suited for MS/RF applications for today’s IoT and smart wearable innovations.

Technology characteristicsShrink technology: NO
Pore voltage1.8V
I/O voltage 3.3V
Shallow Trench Isolation (STI)
Triple well (retrograde NW, PW and optional DNW)
Substrate resistivity 8~12 ohm.cm on <100> P- substrate
Standard Vt, Medium Vt NMOS and medium Vt PMOS, native NMOS
HRI poly resistor
Temperature range -40C to 125C
# of metals: 3 to 6
Interconnect material: AlCu
Interconnect dielectric: FSG
Top metal: 8KA, 20KA or 40KA
RDL: 8KA, limited offer in FAB8
Inductors
MoM
MiM: 1fF/µm2 or 2fF/µm2, mutual exclusive
Passivation: single
Options that need special attentionOTP / MTP
Wafer size8 inch
Deliverables40 dies / wafer
Design toolsCadence CDBA, Cadence OA, TSMC iPDK
Simulation toolsHSPICE, Eldo, Spectre
Verification tools DRCMagma, Cadence, Synopsys, Mentor Graphics
Verification tools LVSMagma, Cadence, Synopsys, Mentor Graphics
Parasitic extraction toolsCadence, Synopsys, Mentor Graphics
P&R toolsCadence, Synopsys
Foundry IPStandard cells: 7-track. Gate density >= 140KGates / mm2
I/O library 3.3V
SRAM: from third party
MPW block sizeMin. 25 mm2, flexible aspect ratio
Mini@sic characteristicsSupported
Block size: 1660µm x 1660µm
3.3V
1P6M 4X1U (U=20KA)
Mimcap 2fF/µm2

0.18µm CMOS Logic or MS/RF, General Purpose 1.8V/5V

TSMC 0.18 µm technology with 6 metal layers. Highly suited for MS/RF applications for today’s IoT and smart wearable innovations.

Technology characteristicsShrink technology NO
Core voltage1.8V
I/O voltage 5V
Shallow Trench Isolation (STI)
Triple well (retrograde NW, PW and optional DNW)
Substrate resistivity 8~12 ohm.cm on <100> P- substrate
Standard Vt, Medium Vt NMOS and medium Vt PMOS
HRI poly resistor
Temperature range -40C to 125C
# of metals: 3 to 6
Interconnect material: AlCu
Interconnect dielectric: FSG
Top metal: 8KA, 20KA or 40KA
RDL: 8KA, limited offer in FAB8
Inductors
MoM
MiM: 1fF/µm2 or 2fF/µm2, mutual exclusive
Passivation: single
Options that need special attentionOTP / MTP
Wafer size8 inch
Deliverables40 dies / wafer
Design toolsCadence CDBA, Cadence OA, TSMC iPDK
Simulation toolsHSPICE, Eldo, Spectre
Verification tools DRCMagma, Cadence, Synopsys, Mentor Graphics
Verification tools LVSMagma, Cadence, Synopsys, Mentor Graphics
Parasitic extraction toolsCadence, Synopsys, Mentor Graphics
P&R toolsCadence, Synopsys
Foundry IPStandard cells: 7-track. Gate density >= 140KGates / mm2
I/O library 3.3V
SRAM: from third party
MPW block size25 mm2, flexible aspect ratio
Mini@sic characteristicsNot supported

0.13µm CMOS Logic or MS/RF, General Purpose

For applications in consumer electronics, computers, mobile computing, automotive electronics, IoT, and smart wearables.

Technology characteristicsShrink technology: NO
Core voltage: 1.2V
I/O voltage: 2.5 or 3.3V
Shallow Trench Isolation (STI)
Wells: Retrograde twin well cmos technology on <100> P-substrate. Substrate resistivity 8-12ohm-cm
Tripple Well, Deep N-well (optional)
Vt options: lvt, svt, hvt,uhvt, native
Temperature range: -40C to 125C
# of metals: 3 to 8 +ALRDL
Interconnect dielectric: FSG
Top metal: 8KA
CMP on STI, contact, via and inter-metal dielectric layers
MoM
Varactors
MS/RF optionsMIM capacitor for MS & RF process: 1fF/µm2
High-Q copper inductor
Top metal: UTM, 33.5K
Single passivation, Dual passivation optional
Wafer size8/12 inch
Deliverables# of dies (no wafer!): 40-dies (8"), 100 dies (12") / wafer
Design toolsPDK: Cadence CDBA and OA, Mentor
Simulation toolsHspice, Eldo, Spectre
Verification tools DRCCadence, Mentor Graphics
Verification tools LVSCadence, Mentor Graphics
Parasitic extraction toolsCadence, Mentor Graphics
P&R toolsCadence, Synopsys
Foundry IP9-track core cell library, with 5V I/O devices, SVt
1.2/3.3V regular,linear universal standard I/O
1.2V/2.5V & 1.2/3.3V Universal Analog I/O compatible with Linear Universal Standard I/O
1.2V/2.5V & 1.2/3.3V , hybrid linear slim I/O library that contains both standard and analog slim I/O
5V tolerant, linear universal standard I/O
1.2V/3.3V, 5V tolerant, staggered universal standard I/O
SRAM compilers from 3rd party
MPW block size25 mm2, flexible aspect ratio
Mini@sic characteristicsNot supported

0.13µm CMOS Logic or MS/RF, Low Power

For applications in consumer electronics, computers, mobile computing, automotive electronics, IoT, and smart wearables.

Technology characteristicsShrink technology: NO
Core voltage: 1.5V
I/O voltage: 2.5 or 3.3V
Shallow Trench Isolation (STI)
Wells: Retrograde twin well cmos technology on <100> P-substrate. Substrate resistivity 8-12ohm-cm
Tripple Well, Deep N-well (optional)
Vt options: lvt, svt, native
Temperature range: -40C to 125C
# of metals: 3 to 8 (CU) (+ALRDL)
Interconnect dielectric: FSG
Top metal: 8KA
CMP on STI, contact, via and inter-metal dielectric layers
MoM
Varactors
MS/RF optionsMIM capacitor for MS & RF process: 1fF/µm2
High-Q copper inductor
Top metal: UTM, 33.5K
Single passivation, Dual passivation optional
Wafer size8/12 inch
Deliverables# of dies (no wafer!): 40-dies (8"), 100 dies (12") / wafer
Design toolsPDK: Cadence CDBA and OA, Mentor
Simulation toolsHspice, Eldo, Spectre
Verification tools DRCCadence, Mentor Graphics
Verification tools LVSCadence, Mentor Graphics
Parasitic extraction toolsCadence, Mentor Graphics
P&R toolsCadence, Synopsys
Foundry IP9-track core cell library
MPW block size25 mm2, flexible aspect ratio
Mini@sic characteristicsNot supported

90nm CMOS Logic or MS/RF, General Purpose

Provide a general-purpose product for applications with a 1.0V core design and with 1.8, 2.5 or 3.3V capable IO’s for digital consumer, Networking , HDD and FPGA

Technology characteristicsShrink technology: NO
Core voltage: 1.0V
I/O voltage: 1.8, 2.5 or 3.3V
Shallow Trench Isolation (STI)
Wells: Retrograde twin well cmos technology on P-substrate
Tripple Well, Deep N-well (optional)
Multiple Vt options (lvt, svt, hvt, native)
Dual gate oxide and tripple gate oxide process
Temperature range: -40C to 125C
# of metals: 3 to 9 (+ALRDL)
Interconnect material: Cu + AlCu pad
LK inter-metal dielectric for thin metal
Top metal: 5.6 KA, 8.5KA
CMP on STI, contact, via and inter-metal dielectric layers
MoM
MS/RF optionsMIM capacitor for MS & RF process: 1.0, 1.5, 2.0 fF/µm2(mutually exclusive)
High-Q copper inductor
Top metal: UTM, 34KA
Varactors
Dual passivation
Options that need special attentionFuse RAM
Wafer size12 inch
Deliverables# of dies (no wafer!): 100 dies / wafer (12")
Design toolsPDK: Cadence CDBA, Cadence OA, Mentor, iPDK
Simulation toolsHspice, Eldo, Spectre
Verification tools DRCCadence, Mentor Graphics
Verification tools LVSCadence, Mentor Graphics
Parasitic extraction toolsCadence, Mentor Graphics
P&R toolsCadence, Synopsys
Foundry IP7,9,14-track core cell library, multi-Vt
1.0V/2.5V &1.0V/3.3V hybrid staggered slim I/O library that contains both standard and analog slim I/O
1.0V/2.5V &1.0V/3.3V linear staggered slim I/O library that contains both standard and analog slim I/O
1.0v/2.5v, 3.3v tolerant, staggered universal standard I/O
1.0V/3.3V, 5V Tolerant, Staggered Universal Standard I/O
SRAM compilers from 3rd party
MPW block size16 mm2, flexible aspect ratio
Mini@sic characteristicsNot supported

90nm CMOS Logic or MS/RF, Low Power

Provide a general-purpose product for applications with a 1.2V core design and with 2.5 or 3.3V capable IO’s for mobile applications like Cellular, WLAN, BT

Technology characteristicsShrink technology: NO
Core voltage: 1.2V
I/O voltage: 2.5 or 3.3V
Shallow Trench Isolation (STI)
Wells: Retrograde twin well cmos technology on P-substrate
Tripple Well, Deep N-well (optional)
Multiple Vt options (ulvt, lvt, svt, hvt, native)
Dual gate oxide and tripple gate oxide process
Temperature range: -40C to 125C
# of metals: 3 to 9 (CU) (+ALRDL)
Interconnect material: Cu + AlCu pad
LK inter-metal dielectric for thin metal
Top metal: 5.6 KA, 8.5KA
CMP on STI, contact, via and inter-metal dielectric layers
MoM
Varactors
MS/RF optionsMIM capacitor for MS & RF process: 1.0, 1.5, 2.0 fF/µm2(mutually exclusive)
Ultra Low Vt
High-Q copper inductor
Top metal: UTM, 34KA
Dual passivation
Options that need special attentionFuse SRAM
Wafer size12 inch
Deliverables# of dies (no wafer!): 100 dies / wafer (12")
Design toolsPDK: Cadence CDBA and OA
Simulation toolsHspice, Eldo, Spectre
Verification tools DRCCadence, Mentor Graphics
Verification tools LVSCadence, Mentor Graphics
Parasitic extraction toolsCadence, Mentor Graphics
P&R toolsCadence, Synopsys
Foundry IP7,9,14-track core cell library, multi-Vt
1.2v/2.5v &1.2V/3.3V Universal Analog I/O compatible with Linear Universal Standard I/O
1.2V/2.5V & 1.2V/3.3V Regular, Linear Universal Standard I/O
1.2V/3.3V, regular, linear standard slim I/O
1.2V/3.3V, hybrid staggered slim I/O library that contains both standard and analog slim I/O
SRAM compilers from 3rd party
MPW block size16 mm2, flexible aspect ratio
Mini@sic characteristicsNot supported

65nm CMOS Logic or MS/RF, General purpose

Popular and well supported node

Technology characteristicsShrink technology: NO
Core voltage: 1.0V
I/O voltage: 2.5V (1.8V underdrive, 3.3V overdrive)
Shallow Trench Isolation (STI)
Wells: Retrograde twin well for low well sheet resistance and better latch-up behavior.
Optional Deep N-Well
<100> P- substrate wafer. Substrate resistivity 8-12ohm-cm
Dual Gate Oxide (1 for core, 1 for IO)
Vt options: lvt, svt, hvt, native
Temperature range: -40C to 125C
# of metals: 3 to 9 Cu + alrdl
Interconnect dielectric: LK
Top metal: 5KA, 9KA, 12.5KA, 34KA
CMP on STI, contact, metals, vias and passivation
MoM
MiM density: 1fF/µm2, 1.5fF/µm2 or 2fF/µm2, mutually exclusive
Passivation: dual layers
Options that need special attentionOTP/MTP
SRAM Cell
Wafer size12 inch
Deliverables# of dies (no wafer!): 100 dies / wafer
Design toolsPDK: Cadence CDBA and OA, TSMC iPDK, Mentor
Simulation toolsHspice, Eldo, Spectre
Verification tools DRCCadence, Mentor Graphics, Synopsys, Magma, TSMC iDRC
Verification tools LVSCadence, Mentor Graphics, Synopsys, Magma
Parasitic extraction toolsCadence, Mentor Graphics, Synopsys
P&R toolsCadence, Synopsys
Foundry IP12-track / 10-track / 9-track core cell libraries, multi-vt, coarse grain
1.0V/2.5V staggered (fail-safe digital, 5V input tolerant digital, hybrid small footprint digital/analog and regular analog) I/O library
SRAM compilers from 3rd party
MPW block size12 mm2
Mini@sic characteristicsNot supported

65nm CMOS Logic or MS/RF, Low Power

Popular and well supported node

Technology characteristicsShrink technology: NO
Core voltage: 1.2V
I/O voltage: 2.5V (1.8V underdrive, 3.3V overdrive)
Shallow Trench Isolation (STI)
Wells: Retrograde twin well for low well sheet resistance and better latch-up behavior.
Optional Deep N-Well
<100> P- substrate wafer. Substrate resistivity 8-12ohm-cm
Dual Gate Oxide (1 for core, 1 for IO)
Vt options: lvt, svt, hvt, mLowvt, native
Temperature range: -40C to 125C
# of metals: 3 to 9 Cu + alrdl
Interconnect dielectric: LK
Top metal: 5KA, 9KA, 12.5KA, 34KA
CMP on STI, contact, metals, vias and passivation
MoM
MiM density: 1fF/µm2, 1.5fF/µm2 or 2fF/µm2, mutually exclusive
Passivation: dual layers
Options that need special attentionOTP/MTP
SRAM Cell
Wafer size12 inch
Deliverables# of dies (no wafer!): 100 dies / wafer
Design toolsPDK: Cadence CDBA and OA, TSMC iPDK, Mentor
Simulation toolsHspice, Eldo, Spectre
Verification tools DRCCadence, Mentor Graphics, Synopsys, Magma, TSMC iDRC
Verification tools LVSCadence, Mentor Graphics, Synopsys, Magma
Parasitic extraction toolsCadence, Mentor Graphics, Synopsys
P&R toolsCadence, Synopsys
Foundry IP12-track / 10-track / 9-track / 7-track core cell libraries, multi-vt, coarse grain
1.2V/2.5V staggered (fail-safe digital, 5V input tolerant digital, hybrid small footprint digital/analog and regular analog) I/O library
1.2V/2.5V linear (digital, hybrid small footprint digital/analog and regular analog) I/O library
SRAM compilers
MPW block size12 mm2
Mini@sic characteristicsSupported
Block size: 2000 μm x 2000 μm
I/O voltage: 2.5V (1.8UD, 3.3OD)
Metal scheme: 1P9M 6X1Z1U (With 14KA ALRDL)
Mimcap: 2 fF

40nm CMOS Logic or MS/RF, General Purpose

Well supported advanced node, 40G = 45GS

Technology characteristicsShrink technology: YES
Core voltage: 0.9V
I/O voltage: 2.5V (1.8V underdrive, 3.3V overdrive) or true 1.8V
Shallow Trench Isolation (STI)
Wells: Retrograde twin well for low well sheet resistance and better latch-up behavior.
Optional Deep N-Well
<110> P- substrate wafer. Substrate resistivity 8-12ohm-cm
Dual Gate Oxide (1 for core, 1 for IO)
Vt options: lvt, svt, hvt, native
Temperature range: -40C to 125C
# of metals: 3 to 10 Cu + alrdl
Interconnect dielectric: ELK
Top metal: 3.1KA, 9KA, 12.5KA, 34KA
CMP on STI, contact, metals, vias and passivation
MoM
Passivation: dual layers
Options that need special attentionOTP/MTP
SRAM Cell
Wafer size12 inch
Deliverables# of dies (no wafer!): 100 dies / wafer
Design toolsPDK: Cadence CDBA and OA, TSMC iPDK
Simulation toolsHspice, Eldo, Spectre
Verification tools DRCCadence, Mentor Graphics, Synopsys, Magma, TSMC iDRC
Verification tools LVSCadence, Mentor Graphics, Synopsys, Magma, TSMC iLVS
Parasitic extraction toolsCadence, Mentor Graphics, Synopsys
P&R toolsCadence, Synopsys
Foundry IP12-track / 9-track core cell libraries, multi-vt, coarse grain
0.9V/1.8V staggered (fail-safe digital, 5V input tolerant digital and regular analog) I/O library
0.9V/2.5V staggered (fail-safe digital, 5V input tolerant digital and regular analog) I/O library
SRAM compilers
MPW block size9 mm2
Mini@sic characteristicsNot supported

40nm CMOS Logic or MS/RF, Low Power

Well supported advanced node

Technology characteristicsShrink technology: YES (90% linear shrink)
Core voltage: 1.1V
I/O voltage: 2.5V (1.8V underdrive, 3.3V overdrive)
Shallow Trench Isolation (STI)
Wells: Retrograde twin well for low well sheet resistance and better latch-up behavior.
Optional Deep N-Well
<110> P- substrate wafer. Substrate resistivity 8-12ohm-cm
Dual Gate Oxide (1 for core, 1 for IO)
Vt options: lvt, svt, hvt, native
Temperature range: -40C to 125C
# of metals: 3 to 10 Cu + alrdl
Interconnect dielectric: ELK
Top metal: 3.1KA, 9KA, 12.5KA, 34KA
CMP on STI, contact, metals, vias and passivation
MoM
Passivation: dual layers
Options that need special attentionOTP/MTP
SRAM Cell
Wafer size12 inch
Deliverables# of dies (no wafer!): 100 dies / wafer
Design toolsPDK: Cadence CDBA and OA, TSMC iPDK, Mentor
Simulation toolsHspice, Eldo, Spectre
Verification tools DRCCadence, Mentor Graphics, Synopsys, Magma, TSMC iDRC
Verification tools LVSCadence, Mentor Graphics, Synopsys, Magma, TSMC iLVS
Parasitic extraction toolsCadence, Mentor Graphics, Synopsys
P&R toolsCadence, Synopsys
Foundry IP12-track / 9-track core cell libraries, multi-vt, coarse grain
1.1V/2.5V staggered (fail-safe digital, 5V input tolerant digital, hybrid small footprint digital/analog and regular analog) I/O library
SRAM compilers
MPW block size9 mm2
Mini@sic characteristicsSupported
Block size: 1920 x 1920 μm (pre-shrink)
I/O voltage: 2.5V (1.8UD, 3.3OD)
Metal scheme: 1P8M 5X2Z (With 14KA ALRDL)

28nm CMOS HPC+ Logic, RF

TSMC 28NM CMOS RF HIGH PERFORMANCE COMPACT MOBILE COMPUTING PLUS 0.9/1.8V

Technology characteristicsShrink technology: YES
Core voltage: 0.9V
I/O voltage: 1.8V
Shallow Trench Isolation (STI)
Wells: Retrograde twin well for low well sheet resistance and better latch-up behavior.
Triple well, Deep N-Well in option
Dual Gate Oxide
Vt options: ulvt, lvt, svt, hvt, uhvt, ehvt
5V HVMOS
HighRes resistors
Temperature range: -40C to 125C
# of metals: 5 to 10 Cu + ALRDL
Interconnect dielectric: ELK
Top metal: 1.9KA, 8.5KA, 11.5KA, 35KA
CMP on STI, contact, via and passivation
MoM capacitor
Passivation: dual layers
Options that need special attentionSRAM Cell
Vt’s: maximum of 4 VT types in one design.
Wafer size12 inch
Deliverables100 dies, no wafer
Design toolsPDK: TSMC iPDK
Simulation toolsHspice, Eldo, Spectre
Verification tools DRCCadence, Mentor Graphics, Synopsys
Verification tools LVSCadence, Mentor Graphics, Synopsys
Parasitic extraction toolsCadence, Mentor Graphics, Synopsys
P&R toolsCadence, Synopsys
Foundry IP12-track / 9-track / 7-track core cell libraries, multi-vt’s
0.9V/1.8V hybrid staggered (fail-safe digital and regular analog) I/O library
SRAM compilers by TSMC , ARM, Synopsys
MPW block size6mm² (on silicon)
Mini@sic characteristicsNot supported

28nm CMOS HPC Logic, RF

TSMC 28NM CMOS RF HIGH PERFORMANCE COMPACT MOBILE COMPUTING 0.9/1.8V

Technology characteristicsShrink technology: YES
Core voltage: 0.9V
I/O voltage: 1.8V
Shallow Trench Isolation (STI)
Wells: Retrograde twin well for low well sheet resistance and better latch-up behavior.
Triple well, Deep N-Well in option
Dual Gate Oxide
Vt options: ulvt, lvt, svt, hvt, uhvt, ehvt
5V HVMOS
HighRes resistors
Temperature range: -40C to 125C
# of metals: 5 to 10 Cu + ALRDL
Interconnect dielectric: ELK
Top metal: 1.9KA, 8.5KA, 11.5KA, 35KA
CMP on STI, contact, via and passivation
MoM capacitor
Passivation: dual layers
Options that need special attentionSRAM Cell
Vt’s: maximum of 4 VT types in one design.
Wafer size12 inch
Deliverables100 dies, no wafer
Design toolsPDK: TSMC iPDK
Simulation toolsHspice, Eldo, Spectre
Verification tools DRCCadence, Mentor Graphics, Synopsys
Verification tools LVSCadence, Mentor Graphics, Synopsys
Parasitic extraction toolsCadence, Mentor Graphics, Synopsys
P&R toolsCadence, Synopsys
Foundry IP12-track / 9-track / 7-track core cell libraries, multi-vt’s
0.9V/1.8V hybrid staggered (fail-safe digital and regular analog) I/O library
SRAM compilers by TSMC , ARM, Synopsys
MPW block size6mm² (on silicon)
Mini@sic characteristicsSupported
Block size: 1570 x 1570 μm (pre-shrink)
Micro-block size: 1110 x 1110 µm (pre-shrink)
I/O voltage: 1.8V
Metal scheme: 1P8M 5X1Z1U (With 28KA UT-ALRDL)
11 mils backlapping

16nm CMOS logic FinFet Compact

EUROPRACTICE has recently extended its portfolio by including a flagship technology TSMC 16nm CMOS logic FinFet Compact 0.8V/1.8V.

Since it is classified as a leading node technology, access to it is subject to review and approval by TSMC.

Technology characteristicsShrink technology: 2% shrink
Core voltage: 0.8V
I/O voltage: 1.8V
Shallow Trench Isolation (STI)
Triple well, Deep N-Well in option
Dual gate oxide
Vt options: hvt, svt, lvt, ulvt, low noise vt
5V HVMOS
TiN High Resistor
N+/P+ metal gate allows symmetrical design of NMOS and PMOS devices
Temperature range: -40C to 125C
# of metals: 6 to 13 Cu plus last metal level in Al pad
Interconnect dielectric: ELK
HD MiM capacitors
Passivation: dual layers
12 inch wafers
Wafer size12 inch
Deliverables100 dies, no wafer
Design toolsPDK: TSMC iPDK
Simulation toolsHspice, Eldo, Spectre
Verification tools DRCCadence, Mentor Graphics, Synopsys
Verification tools LVSCadence, Mentor Graphics, Synopsys
Parasitic extraction toolsCadence, Mentor Graphics, Synopsys
P&R toolsCadence, Synopsys
Foundry IP9-track, 7.5-track body biased core cell libraries with gate lengths of 16, 20 and 24nm
0.8V/1.8V hybrid staggered I/O library
SRAM compilers by TSMC, ARM_Artican, ARM ltd, GUC, Synopsys
MPW block size4mm²
Mini@sic characteristicsNot supported