UMC

Technologies

UMC

Imec offers EUROPRACTICE customers access to the UMC technologies.

CIS180 Image Sensor 1.8V/3.3V 2P4M

0.18 µm CMOS Image Sensor 1.8 V/3.3 V 2P4M Metal Metal Capacitor Process Design Support

Technology characteristicsShrink technology: NO
Core voltage: 1.8V
I/O voltage: 3.3V
Shallow Trench Isolation (STI)
Twin well
Substrate resistivity: 15~25 Ohm.cm on <100> P- substrate
RVt, 1.8V LVt N/PMOS, 3.3V LVt N/PMOS, Zero-Vt NMOS
Temperature range: -40C to 125C
# of metals: 4
Interconnect material: Al
Dielectric: FSG
Top metal: 5KA
Inductors
MiM: 1fF/µm2
Poly/Poly capacitor: 3 fF/µm2
Passivation: single
Wafer size8 inch
Deliverables# of dies: 50 for an MPW, 25 for a mini@sic run
Design toolsCadence CDBA, Laker
Simulation toolsHSPICE, Eldo, Spectre
Verification tools DRCCadence, Mentor Graphics, Synopsys
Verification tools LVSCadence, Mentor Graphics, Synopsys
Parasitic extraction toolsCadence, Mentor Graphics, Synopsys
P&R toolsCadence, Synopsys
Foundry IPFaraday standard cell libraries
Faraday I/O library 3.3V
Faraday memories
MPW block size5mm x 5mm
Mini@sic characteristicsOn request

L180 EFLASH/EE2PROM

UMC 0.18 µm 1.8V/3.3V 1P6M logic process with embedded Flash/EEPROM memories

Technology characteristicsShrink technology: NO
Core voltage: 1.8V
I/O voltage: 3.3V
Shallow Trench Isolation (STI)
Triple well
Substrate resistivity: 15~25 Ohm.cm on <100> P- substrate
Std Vt, 3.3V LVt PMOS, 3.3V LVt NMOS, 1.8V LVt PMOS, 1.8V LVt NMOS, 3.3V zero_Vt NMOS, 14V HV, 6.5V MV
Temperature range: -40C to 125C
# of metals: 6
Interconnect material: Al
Dielectric: FSG
Top metal: 8KA, 12 KA
Inductors
MoM
MiM: 1fF/µm2
Passivation: single
Wafer size8 inch
Deliverables# of dies: 50 for an MPW, 25 for a mini@sic run
Design toolsCadence CDBA, Laker
Simulation toolsHSPICE, Eldo, Spectre
Verification tools DRCCadence, Mentor Graphics, Synopsys
Verification tools LVSCadence, Mentor Graphics, Synopsys
Parasitic extraction toolsCadence, Mentor Graphics, Synopsys
P&R toolsCadence, Synopsys
Foundry IPFaraday standard cell libraries
Faraday I/O library 3.3V
Faraday memories
MPW block size5mm x 5mm
Mini@sic characteristicsNot supported
BumpingOn request

L180 Mixed Mode/RF 1.8V/3.3V 1P6M

UMC L180 MM/RF 1.8V/3.3V 1P6M technology

Technology characteristicsShrink technology: NO
Core voltage: 1.8V
I/O voltage: 3.eV
Shallow Trench Isolation (STI)
Triple well
Substrate resistivity: 15~25 Ohm.cm on <100> P- substrate
Std Vt, 3.3V LVt PMOS, 3.3V LVt NMOS, 1.8V LVt PMOS, 1.8V LVt NMOS, 3.3V zero_Vt NMOS
Temperature range: -40C to 125C
# of metals: 6
Interconnect material: Al
Dielectric: FSG
Top metal: 8KA, 12 KA or 20KA
Inductors
MoM
MiM: 1fF/µm2
Passivation: single
Options that need special attentionOTP
Wafer size8 inch
Deliverables# of dies: 50 for an MPW, 25 for a mini@sic run
Design toolsCadence CDBA, Cadence OA, Laker, Mentor, Tanner, ADS
Simulation toolseldo, hspice, spectre
Verification tools DRCCadence, Mentor Graphics, Synopsys
Verification tools LVSCadence, Mentor Graphics, Synopsys
Parasitic extraction toolsCadence, Mentor Graphics, Synopsys
P&R toolsCadence, Synopsys
Foundry IPFaraday standard cell libraries
Faraday I/O library 3.3V
Faraday memories
MPW block size5mm x 5mm
Mini@sic characteristicsSupported
Block size: 1525µm x 1525µm
I/O voltage: 3.3V
Metal stack: 1P6M with 20KA top metal
Mimcap density 1fF/µm2
BumpingOn request

L130 Logic/Mixed-Mode/RF

0.13 µm Mixed-Mode and RFCMOS 1P8M Metal Metal Capacitor FSG Enhancement Process

Technology characteristicsShrink technology: NO
Core voltage1.2V
I/O voltage 2.5V or 3.3V
Shallow Trench Isolation (STI)
Twin and triple well
Substrate resistivity 15~25 ohm.cm on <100> P- substrate
HS, LL, SP, HS_SP, HS_LL, SP_LL, HS Native Vt, SP Native Vt
Temperature range -40C to 125C
# of metals: 5 to 8
Interconnect material: Cu
Dielectric: FSG
Top metal: 8KA, 20KA
Inductors
MoM
MiM: 1fF/µm2 or 1.5fF/µm2, mutual exclusive
Passivation: single
Wafer size12 inch
Deliverables90 dies / wafer on MPW, 45 dies / wafer on mini@sic
Design toolsCadence CDBA, Laker
Simulation toolsHSPICE, Eldo, Spectre
Verification tools DRCCadence, Mentor Graphics, Synopsys
Verification tools LVSCadence, Mentor Graphics, Synopsys
Parasitic extraction toolsCadence, Mentor Graphics, Synopsys
P&R toolsCadence, Synopsys
Foundry IPStandard cells
I/O library: NA
MPW block size5mm x 5mm
Mini@sic characteristicsSupported
Block size: 1525µm x 1525µm
3.3V
Metal stack: 1P8M2T
Mimcap 1fF/µm2
BumpingAt request

L110AE Logic/Mixed-Mode/RF

0.11 µm Logic and Mixed-Mode 1P8M Metal Metal Capacitor Al Advanced Enhancement Process.

Technology characteristicsShrink technology: YES
Core voltage: 1.2V
I/O voltage: 1.8V/2.5V/3.3V/5V
Shallow Trench Isolation (STI)
Triple well
Substrate resistivity 15~25 ohm.cm on <100> P- substrate
Vt options: HS, SP, LL, HS_SP, HS_LL, SP_LL and HS_SP_LL
Temperature range: -40C~125C
# of metals: 8
Interconnect material: AlCu
Dielectric: USG
Top metal: 20KA or 40KA
Inductors
MoM
MiM: 1.0fF/µm2 or 1.5fF/µm2 or 2.0fF/µm2
Passivation: single
Wafer size8 inch
Deliverables# of dies (no wafer!): 50 on an MPW, 25 on a mini@sic
Design toolsCadence CDBA, Laker
Simulation toolsHSPICE, Eldo, Spectre
Verification tools DRCCadence, Mentor Graphics, Synopsys
Verification tools LVSCadence, Mentor Graphics, Synopsys
Parasitic extraction toolsCadence, Mentor Graphics, Synopsys
P&R toolsCadence, Synopsys
Foundry IPGate density
I/O voltage, OD, UD
RAM/ROM/Dual port/register files)
MPW block size5mm x 5mm
Mini@sic characteristicsNot supported
BumpingOn request

L65N Logic/Mixed-Mode/RF – Standard Performance

65 nm Logic and Mixed-Mode Standard Performance Low-K Process

Technology characteristicsShrink technology: NO
Core voltage1.0V, 1.1V
I/O voltage 1.8V, 2.5V, 2.5_OD3.3V, 3.3V
MOAT
Twin and triple well
Substrate resistivity 7~17 ohm.cm on Epi - substrate
SP_RVT, SP_HVT, SP_LVT
Temperature range -40C to 125C
# of metals: 10
Interconnect material: Cu
Interconnect dielectric: FSG
Top metal: 8kA, 32.5kA
RDL: 12kA, 25kA, 36kA
Inductors
MoM
MiM: 2fF/µm2
Passivation: single
Wafer size12 inch
Deliverables90 samples
Design toolsCadence CDBA, Laker
Simulation toolsHSPICE, Eldo, Spectre
Verification tools DRCCadence, Mentor Graphics, Synopsys
Verification tools LVSCadence, Mentor Graphics, Synopsys
Parasitic extraction toolsCadence, Synopsys, Mentor Graphics
P&R toolsCadence, Synopsys
Foundry IPStandard cells
I/O library: NA
Dummy fillingby Foundry
MPW block size4000µm x 4000µm
MPW Turnaround time16-18 weeks
Mini@sic characteristicsNot supported
BumpingAt request

L65N Logic/Mixed-Mode/RF – Low Leakage

65 nm Logic and Mixed-Mode Low Leakage Low-K Process

Technology characteristicsShrink technology: NO
Core voltage1.2V
I/O voltage 1.8V, 2.5V, 3.3V overdrive
MOAT
Twin and triple well
Substrate resistivity 7~17 ohm.cm on Epi- substrate
LL_RVT, LL_HVT, LL_LVT
Temperature range -40C to 125C
# of metals: 10
Interconnect material: Cu
Interconnect dielectric: FSG
Top metal: 8kA, 32.5kA
RDL: 32.5kA
Inductors
MoM
MiM: 2fF/µm2 Passivation: single
Wafer size12 inch
Deliverables90 samples
Design toolsCadence CDBA, Laker
Simulation toolsHSPICE, Eldo, Spectre
Verification tools DRCCadence, Mentor Graphics, Synopsys
Verification tools LVSCadence, Mentor Graphics, Synopsys
Parasitic extraction toolsCadence, Synopsys, Mentor Graphics
P&R toolsCadence, Synopsys
Foundry IPStandard cells
I/O library: NA
MPW block size16-18 weeks
Mini@sic characteristicsSupported
Block size: 1875µm x 1875µm
2.5V/2.5_OD3.3V
1P8M1T0F1U (U=32.5kA)
Mimcap 2fF
BumpingAt request

40N Logic/Mixed-Mode – Low Power

40 nm Logic and Mixed-Mode Low Power Process

Technology characteristicsShrink technology: NO
Core voltage 0.9V
I/O voltage 1.8V, 2.5V
MOAT
Twin and triple well
Substrate resistivity 10~15 ohm.cm on Epi- substrate
LP_RVT, LP_HVT, LP_LVT, LP_UHVT
Temperature range -40C to 125C
# of metals: 10
Interconnect material: Cu
Interconnect dielectric: FSG
Top metal: 8kA, 12kA, 32.5kA
RDL: 12.5kA, 34kA
MoM
MiM: 2fF/µm2
Passivation: single
Wafer size12 inch
Deliverables90 samples
Design toolsCadence CDBA, Laker
Simulation toolsHSPICE, Eldo, Spectre
Verification tools DRCCadence, Mentor Graphics, Synopsys
Verification tools LVSCadence, Mentor Graphics, Synopsys
Parasitic extraction toolsCadence, Synopsys, Mentor Graphics
P&R toolsCadence, Synopsys
Foundry IPStandard cells
I/O library: NA
MPW block size4000µm x 4000µm
MPW Turnaround time18-20 weeks
Mini@sic characteristicsNot supported
BumpingAt request

28HPC

28 nm Logic and Mixed-Mode High Performance Compact Process

Technology characteristicsShrink technology: NO
Core voltage 1.0, 1.1V
I/O voltage 1.8V, 2.5V
MOAT
Twin and triple well
Substrate resistivity 15~25 ohm.cm on Epi- substrate
UHVT, HVT, RVT, LVT, ULVT
Temperature range -40C to 125C
# of metals: 10
Interconnect material: Cu
Dielectric: FSG
Top metal: 8kA, 12kA, 32.5kA
RDL: 14.5kA, 28kA
MoM
MiM: 2fF/µm2
Passivation: single
Wafer size12 inch
Deliverables90 samples
Design toolsCadence CDBA, Laker
Simulation toolsHSPICE, Eldo, Spectre
Verification tools DRCCadence, Mentor Graphics, Synopsys
Verification tools LVSCadence, Mentor Graphics, Synopsys
Parasitic extraction toolsCadence, Synopsys, Mentor Graphics
P&R toolsCadence, Synopsys
Foundry IPStandard cells
I/O library: NA
Dummy fillingby Foundry
MPW block size4000µm x 4000µm
MPW Turnaround time20-22 weeks
Mini@sic characteristicsNot supported
BumpingAt request