MPW & Mini@sic

Multi Project Wafer (MPW)

High costs of a prototype run can be shared among different customers by combining their designs into one mask set. This technique, known as Multi Project Wafer, reduces the cost of a full prototyping wafer run to 10% or even 5% of the initial price.

MPW Principle
MPW Principle

Mini@sic

The minimum charged design size on regular MPW runs can still be larger than most of the designs created for research purposes. Therefore, the mini@sic principle was introduced:

Several times per year, a minimum area MPW block size is bought and resold in smaller sub-blocks. This solution offers lower prototype fabrication costs than standard MPW runs.

Mini@sic options are available for the following technologies:

amsselected MPW runs
GLOBALFOUNDRIESselected MPW runs for 130nm, 55nm and 22nm nodes
IHPall MPW runs
On Semiconductorall MPW runs, except On Semi 0,18 µm
TSMCselected MPW runs for 0.18µm, 65nm, 40nm and 28nm CMOS mixed signal RF
UMCselected MPW runs for 0.18µm, 0.13µm and 65nm CMOS mixed signal RF
X-FABselected MPW runs for XH018 and XT018

For more information, please check our mini@sic run schedule and price list

Examples of mini@sic blocks in different technologies
Examples of mini@sic blocks in different technologies

Microblock

In 2018, EUROPRACTICE has further lowered the entry barrier for using advanced technologies by introducing the concept of a Microblock for the 28nm technology from TSMC. The Microblock size is even smaller than the one provided by the mini@sic solution: 1110 x 1110 microns (designed area – pre-shrink). These designs can be placed on any of the 28nm-mini@sic runs. However, note that in case of only one Microblock request, there is no commitment that the run will be launched.

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