MEMSCAP

Technologies

MEMSCAP

MEMSCAP offers three multi-mask MEMS processes in MUMPs® : PolyMUMPs, SOIMUMPs, and PiezoMUMPs.

PolyMUMPsSOIMUMPsPiezoMUMPs
Fixed die size (mm²)10 x 1010 x 1011 x 11
“Standard Die Site”Active area (mm²)9.8 x 9.89 x 99 x 9
Number of dies delivered151515
HF releasepossibleNot applicableNot applicable
Optional post processingHF release and CO2 DrypossibleNot applicableNot applicable
SubdicingpossibleBy design or optional laser dicingBy design or optional laser dicing

PolyMUMPs

PolyMUMPs TM is the industry’s longest-running MEMS multi-project wafer service, with over a decade of history. Many universities use the service today as a way to teach beginning MEMS design at the undergraduate level, using PolyMUMPs as the “example” process.

 

PolyMUMPs TM is a three-layer polysilicon surface and bulk micromachining process, with 2 sacrificial layers and one metal layer. Eight mask levels create 7 physical layers. The minimum feature size in PolyMUMPs is 2µm.

Technology characteristicsActive area (mm2): 9.8 x 9.8
Polysilicon/ gold
Surface micromachining
Special featuresPolysilicon Surface Micomachining.
One poly ground layer, two structural poly layers, one gold metal layer, two oxide release layers.
Application areaMEMS, micromechanics, MOEMS

SOIMUMPs

SOIMUMPs TM uses a SOI wafer with a thickness of 10µm or 25µm and allows the designer to pattern and etch both sides of the SOI wafer down to the buried oxide, enabling through-holes to pass light through. Two metal layers, one for bond pads and one for reflectivity, are included in the Standard Process. The minimum feature size in SOIMUMPs TM is 2µm.

Technology characteristicsActive area (mm2): 9 x 9
Special featuresDRIE (Deep Reactive Ion Etching) on Silicon-On-Insulator wafer
Application areaMEMS, micromechanics, MOEMS

PiezoMUMPs

The PiezoMUMPs TM process is based on the SOIMUMPs process with 10µm SOI thickness. Its distinguishing feature is a piezoelectric layer of AlN. Top-contact to the piezoelectric layer and the SOI is enabled by means of a patterned layer of Metal. Patterning of the oxide layer that separates the SOI and the AlN allows for contact between the latter. Patterning of the SOI and openings in the handle silicon are available as is the case for SOIMUMPs TM.

Technology characteristicsActive area (mm2): 9 x 9
Special featuresDRIE (Deep Reactive Ion Etching) on Silicon-On-Insulator wafer + piezoelectric layer
Application areaMEMS, micromechanics, MOEMS

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