Technologies > TSMC Overview


TSMC 0.18 um technology overview (MPW):

Technology Logic MS/RF
Geometry 0.18um 0.18um
Device Application General Purpose MS CMOS
Core Voltage (V) 1.8 1.8
I/O Voltage (V) 3.3 3.3
Poly Layers 1 1
Metal Layers (Min) 3 3
Metal Layers (Max) 6 6
RO Speed (ps/gate) 28 28
BEOL Dielectric FSG(K=3.6) FSG(K=3.6)
BEOL Metal Al Al
PROCESS FEATURE

Well Formation SSR SSR
Isolation STI STI
Gate Materials Silicide Silicide
Silicide Material Co-salicide Co-salicide
Gate Dielectric tox(core) 32A 32A
Gate Dielectric tox(I/O) 70A 70A
Emb-6T SRAM cell (um2) 4.65/4.89 4.65/4.89
DEVICE CHART (CORE)

nMOS--Isat (uA/um) 600 600
nMOS--Vt(V) 0.42 0.42
nMOS--Ioff_max (nA/um) 0.1 0.1
pMOS--Idsat (uA/um) 260 260
pMOS--Vt(V) -0.5 -0.5
pMOS--Ioff_max (nA/um) 0.1 0.1
DEVICE CHART (I/O)

Vdd(V) 3.3 3.3
nMOS--Isat (uA/um) 600 600
nMOS--Vt(V) 0.72 0.72
nMOS--Ioff_max (nA/um) 0.1 0.1
pMOS--Idsat (uA/um) 300 300
pMOS--Vt(V) -0.74 -0.74
pMOS--Ioff_max (nA/um) 0.1 0.1
MS/RF PROCESS MODULE

Core transistor Vt N/A Nominal, Medium, Native
PiP N/A N/A
MiM N/A Q for C = 0.9pF C = 1.00fF/um2 @ 2.4 GHz > 50
Inductor N/A 2.0um (Al) Q for L = 4nH @ 2.4 GHz > 9
Hi Resistors N/A 1050 Ohm/Sq
Varactor N/A MOS and Junction Varactors available
Triple well N/A Available
BJT DEVICE

Hfe N/A N/A
VA(V) N/A N/A
BV ceo(V) N/A N/A
Ft(GHz) N/A N/A
Fmax(GHz) N/A N/A
Ipeak(mA) N/A N/A
MORE FEATURES

Default # of masks
(exclusive opt. masks)
26 26
# optional masks 5 9
All Optional masks PW3V/NW3V,
1TRAM-VTP,
ESD,FW,PM
DNW,1TRAM-VTP,VTM_N,
VTM_P,HRI,ESD,CTM,FW,PM
EP MPW optional masks ESD,FW,PM DNW,ESD,CTM,FW,PM
Made in Fab Fab8,Fab11,
SSMC,Fab3 (all 8inch)
Fab8,Fab11,
SSMC,Fab3 (all 8inch)
DESIGNKITS

Available PDK for Cadence 1 PDK for Logic and MS/RF (CR018G)
Available PDK for Mentor N/A
Available iPDK for Synopsys 2 iPDK for MS/RF (CR018G, CR018GPII)

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