EM Microelectronic


Since 2020, EUROPRACTICE starts to provide access to the EMALP18 logic technology of EM Microelectronic.

0.18µm EMALP18 logic

Technology characteristicsMet. layers: 4/5. Option B -4ML or Option M -5ML
Minimum Gate length: 180nm [drawn]
Dual Gate Oxides: 3.0nm ThinGOX [1.98V max] and 6.5nm DualGOX [3.63V max]
FEOL isolation: Non Epi or p-Epi substrate [16-24Ω.cm], STI [Shallow trench isolation]
Supply voltage: 1.8V or 3.3V
Special featuresEKV models with parameters for near/sub Vth operations
Digital cell library optimized for Low Power/Low Voltage
I/O pads library with low leakage ESD protections
Application areaUltra-Low Power, Ultra-Low Voltage
Analog Designs (low leakage, low noise, pairing)
Mixed signal (100kGates/mm2)
Low current (nA bias), Low voltage (down to 0.4V)
Design kits version0.7
Frontend Backend toolsCadence IC 6.1.7
Simulation toolsSpectre (Cadence), Incisive (Cadence), CustomSim XA (Synopsys)
Verification toolsPVS (Cadence)
Parasitics extraction toolsQRC (Cadence)
Place route toolsInnovus (Cadence)
Turnaround Time10-12 weeks from MPW run deadline to packaged parts

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