GLOBALFOUNDRIES

Technologies

Global Foundries

EUROPRACTICE provides access to the following GLOBALFOUNDRIES technologies.

GF SiGe 8XP

GF’s SiGe 8XP technology drawn at 130nm features low noise figures, high linearity, gain, breakdown and operating voltages, together with simplified impedance matching and excellent thermal stability. Advanced SiGe heterojunction bipolar transistors (HBTs) provide superior low-current and high-frequency performance while enabling the technology to operate at high junction temperatures.

Technology characteristicsCore voltage: 1.2V / 2.5V
I/O voltage: 1.5 / 1.8V / 2.5V / 3.3V
TSV
Metal layers: 5 - 7 of Cu and AI
Thick Al and Cu “MA” add-on module for high Q inductors
Forward Bias, PIN and Schottky Barrier Diodes
High performance SiGe NPN transistors (fT/fmax 250/340GHz)
High breakdown fT= 78GHz, 3.2V BVceo
Temperature Range: -55°C to 125°C
Device offerings: SchottkyDiode, P+ poly resistors, Thin oxide NMOS varactor/ decoupling capacitor, Spiral inductors, Transmission lines, mmWave passive elements, eFuse, Triple-well NFETs, PIN Diode, Hyper abrupt (HA) varactor, MIM capacitor, Dual MIM (3 fF/μm2), High-RsRR poly resistor, TaNmetal KQ resistor, True triple well (T3) FET
Wafer size12inch
Manufacturing locationFab9 - Burlington, Vermont, USA
Deliverables50 bare dies
Signoff toolsCadence, Mentor Graphics
Foundational IPs Standard cell libraries: GLOBALFOUNDRIES
GPIO : GLOBALFOUNDRIES
SRAM : ARM / GLOBALFOUNDRIES

The ARM IPs have to be requested directly at ARM via DesignStart portal

For GLOBALFOUNDRIES IPs contact Fraunhofer IIS

Dummy fillingTo be done by the customer
MPW block size9mm² with a min. edge length of 1mm, flexible aspect ratio
Turnaround timeca. 6 months
mini@sic characteristicsNot supported
BumpingCu Pillar and SnAg

GF 130BCDLite

The GF 130BCDLite process is tailored for cost-effective mobile/consumer applications: DC-DC, AC-DC, PMIC, Wireless and Quick Charging.

Technology characteristicsCore and I/O Voltage:1.5V/5V/30V
8-12 Ω-cm p-type substrate (noise isolation)
Poly layers: 1, Metal layers: 4-8 of Cu
Top metal thickness: 30kA and/or 9kA
Recommended metal stack on MPW: 1P7M TM30K
Metal: Cu, AI(RDL)
Device offeringss: High gain MOSFETs with Regular and NativeVt, BJTs, Diodes, Single Mask MIM, Resistors, eFuse, Inductors, ESD, Pads.
RF Devices: MOSFETs, LDMOS, Capacitors and Diodes
Special devices: MTP, OTP, eFlash
Passivation: Single or Dual
Wafer size12 inch
Manufacturing locationFab7 - Woodlands, Singapore
Deliverables50 dies for general MPW, 25 dies for mini@sic run
Signoff toolsCadence, Synopsys, Mentor Graphics
Foundational IPs Standard cell libraries: ARM
GPIO : GLOBALFOUNDRIES
SRAM : ARM
Dummy fillingTo be done by the customer
MPW block size9mm² with a min. edge length of 1mm. flexible aspect ratio
MPW Turnaround timeca. 5 months
mini@sic characteristicsSupported
Block size: 1750µm ×1750µm (incl. Crackstop)
BEOL stack: 1P7M_30kA
PPOLYF_U HIGH SHEET RESISTANCE: 2k
MIMCAP OPTION: 1p0f_SM
Interconnect: Wirebond
BumpingAvailable only for general MPW (Solder bump)

GF 130LP

This comprehensive, highly-configurable and production-proven 130nm Low Power process enables integration of logic, RF, analog and non-volatile memory to provide a cost effective solution.

Technology characteristicsCore voltage: 1.2V / 1.5V
I/O voltage: 1.8V / 2.5V / 3.3V
Poly layers: 1, Metal layers: 2-8
ESD mask for I/O ESD protection circuitry
For analog/RF processes, the following options are available: Deep Nwell, Capacitors, Resistors, Multi-Vt transistors, Inductors
Single or Dual passivation
Wafer size12inch
Manufacturing locationFab7 - Woodlands, Singapore
Deliverables50 bare dies
Signoff toolsMentor Graphics
Foundational IPsStandard cell libraries: ARM
GPIO : Aragio
SRAM : ARM / Synopsys
Dummy fillingTo be done by the customer
MPW block size9mm² with a min. edge length of 1mm, flexible aspect ratio
MPW Turnaround timeca. 5 months
mini@sic characteristicsNot supported
BumpingSolder bump

GF 55LPx-NVM

Built on the 55nm Low Power extended (LPx) base platform with 1.2V and 2.5V CMOS logic, the 55LPx-NVM offers consumer and automotive grade embedded NVM for MCU, IoT, NFC, Bluetooth and WiFi applications. This module offers high density eFlash and HV devices in addition to the base platform features such as DG I/O, multi-Vt transistors, SRAM, DNwell and MIMCaps.

Technology characteristicsCore voltage: 1.2V
I/O voltage: 1.8V/2.5V/3.3V
Poly layers: 1,Metal layers: 6-8
Metal: Cu, AI(LB)
Polyimide or hard-dielectric final passivation
Core transistor Vt: High Vt, Low Vt, Std Vt, Super low Vt, Super High Vt
Poly and diffusion resistors,OP resistors
NFET in n-well, PFET in p-well capacitor, VN BEOL capacitor, MIM, APMOM
EDMOS: 5V N/P,Body Iso-N, Native FET: 1.2V N; 2.5V N
Electrically programmable fuse, Embedded flash and high voltage option
Ultra Thick Metal layer 3 µm thickness Cu layer
1K/2K ohm/sq Poly resistor with HR mask
Temperature range:-40°c to 125°c
Wafer size12inch
Manufacturing locationFab7 - Woodlands, Singapore
Deliverables50 bare dies
Signoff toolsMentor Graphics
Foundational IPsStandard cell libraries: ARM / Silvaco
GPIO : Aragio
SRAM : ARM / Moblie Semi
Dummy fillingTo be done by the customer
MPW block size9mm² with a min. edge length of 1mm, flexible aspect ratio
MPW Turnaround timeca. 5 months
mini@sic characteristicsNot Supported
BumpingCu Pillar and SnAg

GF 55LPe-RF

Built on the GLOBALFOUNDRIES’ low power enhanced (LPe) platform, the 55nm RFCMOS technology combines the benefits of a rich baseline logic technology and IP ecosystem with world-class RF features and PDKs, enabling a seamless transition to digital logic SoCs with higher levels of RF integration. Using a multi-Vt baseline logic process the 55nm LPe-RF technology adds RF-specific features such as Deep n-well devices, LDMOS/EDMOS FETs, Parasitic bipolar devices, MOS/HA varactors, Precision resistors, MIMcaps/MOMcaps, Inductors and Thick metals.

Technology characteristicsCore voltage: 1.2V
I/O voltage: 1.8V/2.5V/3.3V
Temperature range:-40°c to 125°c
Poly layers: 1, Metal layers: 6-8
Metal: Cu, AI(LB)
Polyimide or hard-dielectric final passivation
Core transistor Vt: High Vt, Low Vt, Std Vt
Vertical PNP and NPN bipolar transistor
HR poly resistor, OP, N-well and salicide resistors
NFET in n-well,PFET in p-well capacitor,VN BEOL capacitor
APMOM, 5V LDMOS, 5V isolation EDMOS, SRAMs
Electrically programmable eFuse, Native Inductors (2x/4x wires), 3µm thick Cu wire
Legacy MIMICAP
Wafer size12inch
Manufacturing locationFab7 - Woodlands, Singapore
Deliverables50 bare dies
Signoff toolsMentor Graphics
Foundational IPsStandard cell libraries: ARM / Synopsys
GPIO : Aragio / Innopower
SRAM : ARM / Synopsys / Innopower
Dummy fillingTo be done by the customer
MPW block size9mm² with a min. edge length of 1mm, flexible aspect ratio
MPW Turnaround timeca. 5 months
mini@sic characteristicsNot Supported
BumpingCu Pillar and SnAg

GF 45RFSOI

45RFSOI takes advantage of a 45nm partially-depleted SOI server-class technology base that has been extensively evaluated for use in mmWave applications and in high volume production at multiple GF fabs since 2008. Today, this baseline process has RF-centric enablement, topped with device and technology additions, including thick copper and dielectric back-end-of-line (BEOL) features which enable 45RFSOI to handle the demanding performance requirements of 5G solutions.

Technology characteristicsHigh-resistivity substrate ≥7500 Ω-cm
Three BEOL STACK options: 7 or 8 Levels of Cu Wiring and Thick Al LD or LB
Operating junction temperature: -40°C to 125°C
VDD of 0.9 V or 1.0 V (thin oxide)
Two gate oxide thicknesses
High density / High Q MIMcap, High-value resistor
RF and mmWave offering: Inductors, Microstrip, Coplanar Waveguides, Passives
Fuse: eFuse
Wafer size12inch
Manufacturing locationFab10 - East Fishkill, New York, USA
Deliverables50 dies for general MPW, 25 dies for mini@sic run
Signoff toolsCadence, Mentor Graphics
Foundational IPsStandard cell libraries: ARM
GPIO : ARM
SRAM : N/A
Dummy fillingTo be done by the customer
MPW block size9mm² with a min. edge length of 1mm, flexible aspect ratio
MPW Turnaround timeca. 5.5 months
mini@sic characteristicsSupported
Block size:1500µm x 1500µm (incl. Chipguardring)
BEOL stack: Option #18 (8LM_3Mx_1Cx_1Ux_2Ox_LD)
Interconnect: Inline Wirebond
Turnaround time: ca. 6 months
BumpingAvailable only for general MPW (Cu Pillar and SnAg)

GF 40LP-RF/mmWave

The GF 40LP process technology platform is ideal for power- and price-sensitive mobile and wireless applications with flexible mixed-technology options for RF, low voltage and automotive. The process also enables mmWave solutions for applications that require greater than 30GHz operation.

Technology characteristicsCore voltage:1.1V
I/O voltage:1.5V/1.8V(Medium gate oxide), 1.8V/2.5V/3.3V (Thick gate oxide)
Poly layers: 1, Metal layers: 6-8
3 μm thickness copper layer for Inductors
Temperature range:-40°c to 125°c
Core transistor Vt: High Vt, Low Vt, Std Vt, Super-low Vt
Regular-Vt NFET/PFET, Low-Vt NFET/PFE
Thin/Thick-oxide NCAP, Thin/Thick-oxide PCAP
APMOM,P Poly Resistor,Inductor,Transmission Line
Precision resistors, MIMcaps/MOMcaps, Inductors, Thick metals and Transmission lines.
Recommended Metal Stack on MPWOption # 12 (6L1x_1T6x_1T18x_LB)
Wafer size12inch
Manufacturing locationFab7 - Woodlands, Singapore
Deliverables50 bare dies
Signoff toolsCadence, Synopsys, Mentor Graphics
Foundry IP Standard cell libraries: ARM / Synopsys
GPIO : Aragio
SRAM : ARM / Synopsys
Dummy fillingTo be done by the customer
MPW block size9mm² with a min. edge length of 1mm, flexible aspect ratio
MPW Turnaround timeca. 5 months
mini@sic characteristicsNot Supported
BumpingCu Pillar and SnAg

GF 28SLPe

The GLOBALFOUNDRIES 28SLPe process technology platform is optimized for power, performance and die cost. 28SLPe utilizes optical 0.9x shrink of designs drawn at 32nm dimensions.

Technology characteristicsCore voltage:1V
I/O voltage:1.5V/1.8V
1 poly and 6 - 11 levels of all Copper metal, plus Aluminum top layer metal
3 μm thickness copper layer for Inductors
Temperature Range: -40°C to 125°C
Vt Options: SLVt, LVt, RVt, HVt
Device offerings: Standard FETs, Zero-Vt NFETs, BJTs, eFuse
Resisitors:N+,P+ diffusion and N+,P+ polysilicon silicided,Nwell
N+ diffusion and p+ polysilicon OP,High-precision p+ polysilicon OP
Capacitors:Thin, Medium (EG) oxide NCAP, PCAP, VNCAP or APMOM
Different devices available for eFlash designs
Recommended Metal Stack on MPWOption #2 (6U1x_2T8x_LB)
Wafer size12inch
Manufacturing locationFab1 - Dresden, Germany
Deliverables50 bare dies
Signoff toolsCadence, Synopsys, Mentor Graphics
Foundry IP Standard cell libraries: ARM
GPIO : Aragio
SRAM : ARM
Dummy fillingTo be done by the customer
MPW block size9mm² with a min. edge length of 1mm, flexible aspect ratio
MPW Turnaround timeca. 4.5 months
mini@sic characteristicsNot Supported
BumpingCu Pillar and SnAg

GF 22FDX

GLOBALFOUNDRIES 22nm FD-SOI transistor technology delivers FinFET-like performance and energy-efficiency, including up to 70% lower power vs. 28nm. The simultaneous high Ft /high Fmax, high self gain and high current efficiency of 22FDX enables efficient, ultra low power analog/RF/mmWave designs. The process offers reference flow for back-gate biasing and RF BEOL with ultra thick metal stacks. The eMRAM module supports fully integrated, versatile memory for storage and compute for IoT and MCU.

Technology characteristicsNon-shrink process
Core voltage: 0.8V
I/O voltage: 1.2V/1.5V/1.8V, LDMOS @ 3.3V/5V/6.5V
1 poly and 6 - 10 levels of all copper metal, plus thick aluminum top layer metal
6 Vt options: eLVt, SLVt, LVt, RVt, HVt, UHVt
Qualified for Automotive Grade 1 (-40°C to 150°C)
Device offerings: Standard FETs, Diodes, BJTs, Passives (Resistors, AP/SP MOM, eFuse, Varactor, Parasitic Caps), SRAM (ULL, HD, SP, DP), ESD
RF/mmWave support: FETs, Resistor, Inductor, Varactor, APMOM, Tx Line
Special offering: eMRAM
Wafer size12inch
Manufacturing locationFab1 - Dresden, Germany
Deliverables50 dies for general MPW, 25 dies for mini@sic run
Signoff toolsCadence, Synopsys, Mentor Graphics
Foundational IPsStandard cell libraries: Synopsys
GPIO : Synopsys
SRAM : Synopsys
Double patterning and Dummy fillingTo be done by the customer
MPW block size9mm² with a min. edge length of 1mm, flexible aspect ratio
MPW Turnaround timeca. 3.5 months
mini@sic characteristicsSupported
Block size:1250µm x 1250µm (incl. Crackstop)
BEOL stack: Option #19 (10M_2Mx_5Cx_1Jx_2Qx_LB)
Interconnect: Inline Wirebond
Turnaround time: ca. 4.5 months
BumpingAvailable only for general MPW (Cu Pillar and SnAg)

GF 12LP+

The 12nm GLOBALFOUNDRIES 12LP+ FinFET process technology platform is ideal for high-performance, power-efficient SoCs in demanding, high-volume applications. 3D FinFET transistor technology provides best-in-class performance and power with significant cost advantages from 12nm area scaling. The 12LP+ technology can provide up to 20% higher device performance and 36% lower total power compared to the 12LP technology.

Technology characteristicsBased on 14LPP technology
Dual STI
Core voltage: 0.8V
I/O voltage: 1.2V / 1.35V / 1.5V / 1.8V
BEOL Stack options: 8ML / 9ML / 10ML / 11ML / 13ML
SLVT, LVT, RVT, HVT, DDB, SDB, Single Fin Logic
Device offerings: ESD diodes, vertical BJT, VNCAP, Standard MIM, Adv MIM, Inductors, Precision MOL Resistor, eFuse
Wafer size12inch
Manufacturing locationFab8 - Malta, New York, USA
Deliverables50 bare dies
Signoff toolsCadence, Mentor Graphics, Synopsys
Foundational IPsStandard cell libraries: ARM
GPIO : ARM
SRAM : ARM
Double patterning and Dummy fillingTo be done by the customer
MPW block size9mm² with a min. edge length of 1mm, flexible aspect ratio
MPW Turnaround timeca. 5.5 months
mini@sic characteristicsNot supported
BumpingCu Pillar and SnAg

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