EUROPRACTICE provides access to imec pathfinding PDK (P-PDK) to facilitate the creation of virtual digital designs in advanced CMOS technologies for 2nm and beyond. Imec N2 P-PDK endeavours to bridge the gap between design and technology communities. Built on the imec Logic roadmap, it contains a library of electrically characterized logic standard (std) cells with layout compliant to lithography defined design rules. The electrical performance of the library is obtained from circuit simulations using in-house developed models for devices and interconnects. These models are themselves based on process and TCAD simulations calibrated with silicon data.
The imec N2 Digital CMOS kit is based on the imec N2 technology node process assumptions. It features gate-all-around nanosheet devices and provides the flexibility of a Front-Side and a backside PDN. It contains a library of 102 electrically characterized logic standard (std) cells.
The logic library is built around a 6 track standard cell architecture and the devices contain a stack of 4 nanosheets.
In terms of ground rules, the gate pitch (CPP) is 48nm and the minimum metal pitch (MP) is 22nm. The backside PDN library contains built-in power connections through nano-TSVs to the backside power rails.
The virtual P-PDK contains the necessary infrastructure and design kits for digital design including:
