SCHEDULES & PRICES

2024

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Schedules 2025

2025 RUN SCHEDULES AND PRICES

On this page you can find General MPW and mini@sic run schedules and prices for 2025.

If you need the 2024 schedules, please click here.

There are two prices in the EUROPRACTICE lists: Discounted and Standard.

DISCOUNTED PRICE

Three conditions should be met for Discounted prices:

Customer is an academic institution or a research facility from one of the 27 EU countries together with Albania, Armenia, Azerbaijan, Bosnia-Herzegovina, Georgia, Iceland, Israel, Liechtenstein, North Macedonia, Moldova, Montenegro, Norway, Switzerland, Turkey, Serbia, the UK and Ukraine.
Customer is a registered EUROPRACTICE member who has paid the Full-IC annual membership fee.
The intended design will be done for educational purposes or for publicly funded research.

STANDARD PRICE

Standard prices apply to all other customers.

To reserve your seat on a run, please register your design in the Registration Form or contact the EUROPRACTICE partner responsible for the technology.

Fraunhofer IISB		Jan	Feb	Mar	Apr	May	Jun	Jul	Aug	Sep	Oct	Nov	Dec
4H-SiC CMOS HIGH TEMPERATURE			7

Important notes: Dates are GDS submission deadlines. Design registration must be done at least 4 weeks in advance.

The first design submission (for our review and feedback) must be done on January 10, 2025. Fab-in: March 7, 2025.

For new PDK download please ask virtual-asic@iis.fraunhofer.de

Fraunhofer IISB Pricelist		Standard EUR / block	Discount EUR / block
4H-SiC CMOS HIGH TEMPERATURE (2.5mm x 5mm)¹		10,900	9,900
4H-SiC CMOS HIGH TEMPERATURE (5mm x 5mm)²		21,250	19,250

Important notes:
¹Max. design surface: 2.35mm x 4.85mm

²Max. design surface: 4.85mm x 4.85mm

Larger chip sizes and pricing are available on request.

GLOBALFOUNDRIES MPW	Jan	Feb	Mar	Apr	May	Jun	Jul	Aug	Sep	Nov	Dec
GLOBALFOUNDRIES SiGe 8XP			4						2		8
GLOBALFOUNDRIES 130nm BCDlite – Gen2	1								9
GLOBALFOUNDRIES 55 nm BCDlite			10			25			24		25
GLOBALFOUNDRIES 45RFE		11							2
GLOBALFOUNDRIES 45nm RFSOI	7						8
GLOBALFOUNDRIES 45nm SPCLO – Silicon Photonics				8				19			10
GLOBALFOUNDRIES 28 nm SLPe	27				20				27
GLOBALFOUNDRIES 22 nm FDSOI	13		3	21	12	9		4	30	15
GLOBALFOUNDRIES 12 nm LP+			12			11			10

Important notes: Dates are Registration deadlines after which designs cannot be accepted.

Final GDSII file must be submitted within 6 weeks after this date.

Dates in red are preliminary.

A cancellation fee is applicable if the registration is cancelled later than 2 weeks after the Registration deadline or if the customer is unable to provide a DRC-clean GDS before the Tapeout deadline.

GLOBALFOUNDRIES MPW Pricelist	Standard EUR / mm²	Discounted EUR / mm²
GLOBALFOUNDRIES SiGe 8XP	4,230 ¹	4,050 ¹
GLOBALFOUNDRIES 130 nm BCDlite	1,710 ²	1,620 ²
GLOBALFOUNDRIES 55 nm BCDlite	4,950 ¹	4,680 ¹
GLOBALFOUNDRIES 45RFE	9,180 ¹	8,820¹
GLOBALFOUNDRIES 45RFSOI	9,180 ¹	8,820¹
GLOBALFOUNDRIES 45nm SPCLO -Silicon Photonics (price per fixed block 5mm x 5mm)	231,000	220,000
GLOBALFOUNDRIES 28 nm SLPe	10,890 ³	10,350 ³
GLOBALFOUNDRIES 22 nm FDSOI	16,110 ³	15,300 ³
GLOBALFOUNDRIES 12 nm LP+	26,460 ³	25,200 ³

Important notes:

¹ Price = area (mm²) * price/mm² with min. fabrication cost equivalent to 12 mm². Any edge length between 1.0 mm to 11 mm is possible.

The mentioned die size is referred to the Pre-Shrink die size.

² Price = area (mm²) * price/mm² with min. fabrication cost equivalent to 25 mm². Any edge length between 1.0 mm to 11 mm is possible.

The mentioned die size is referred to the Pre-Shrink die size.

³ Price = area (mm²) * price/mm² with min. fabrication cost equivalent to 9 mm². Any edge length between 1.0 mm to 11 mm is possible.

The mentioned die size is referred to the Pre-Shrink die size.

GLOBALFOUNDRIES mini@sic	Jan	Feb	Mar	Apr	May	Jun	Jul	Aug	Sep	Nov	Dec
GLOBALFOUNDRIES SiGe 8XP			4						2		8
GLOBALFOUNDRIES 130nm BCDlite – Gen2	1								9
GLOBALFOUNDRIES 55 nm BCDlite			10			25			24		25
GLOBALFOUNDRIES 45RFE		11							2
GLOBALFOUNDRIES 45nm RFSOI	7						8
GLOBALFOUNDRIES 45nm SPCLO – Silicon Photonics				8				19			10
GLOBALFOUNDRIES 28 nm SLPe	27				20				27
GLOBALFOUNDRIES 22 nm FDSOI	13		3	21	12	9		4	30	15
GLOBALFOUNDRIES 12 nm LP+			12			11			10

Important notes: The mini@sic model of GlobalFoundries is available only for universities and research institutes.

Dates are Registration deadlines after which designs cannot be accepted.

Final GDSII file must be submitted within 6 weeks after this date.

Dates in red are preliminary.

GLOBALFOUNDRIES mini@sic Pricelist	Standard EUR / mm²	Discounted EUR / mm²
GLOBALFOUNDRIES SiGe 8XP	6,660 ¹	6,300 ¹
GLOBALFOUNDRIES 130nm BCDlite – Gen2	2,880 ²	2,700 ²
GLOBALFOUNDRIES 55 nm BCDlite	7,290 ¹	6,930 ¹
GLOBALFOUNDRIES 45RFE	11,520³	10,980 ³
GLOBALFOUNDRIES 45RFSOI	11,520³	10,980 ³
GLOBALFOUNDRIES 45nm SPCLO -Silicon Photonics	147,000 ⁴	140,000 ⁴
GLOBALFOUNDRIES 28 nm SLPe	15,865 ³	15,105 ³
GLOBALFOUNDRIES 22 nm FDSOI	21,712 ³	20,700 ³
GLOBALFOUNDRIES 12 nm LP+	33,120 ³	31,500 ³

Important notes:

¹ Price = area (mm²) * price/mm² with min. fabrication cost equivalent to 2 mm². The mentioned die size is referred to the Pre-Shrink die size.

² Price = area (mm²) * price/mm² with min. fabrication cost equivalent to 4 mm². The mentioned die size is referred to the Pre-Shrink die size.

³ Price = area (mm²) * price/mm² with min. fabrication cost equivalent to 1 mm².The mentioned die size is referred to the Pre-Shrink die size.

⁴ Price = fixed block size of 5mm x 2.455mm or 2.455mm x 5mm.

TSMC MPW	Jan	Feb	Mar	Apr	May	Jun	Jul	Aug	Sep	Oct	Nov	Dec
TSMC 0.13µm CMOS BCD plus (12-inch)	29				7		23				5
TSMC 0.13µm CMOS Logic or MS/RF, GP or LP (12-inch)	29				7		23				5
TSMC 90nm CMOS Logic or MS/RF, GP or LP						11						10
TSMC 65nm CMOS Logic or MS/RF, GP or LP		5		2	21			27		22
TSMC 40nm CMOS Logic or MS/RF, LP (no triple gate oxide)		5	5	2 23	28		23	27	24	22	19
TSMC 40nm CMOS Logic or MS/RF, GP (no triple gate oxide)			5	23				27
TSMC 28nm CMOS Logic or RF HPC/HPC+		5	12	23	28		2 30		3	29	26
TSMC 22nm CMOS Logic or RF ULL		19	26	23		25		20		1 22
TSMC 16nm CMOS Logic or RF FinFET Compact		5		2	28		23			1	26
TSMC 7nm CMOS Logic or RF FinFET	Run planned for 18 December 2024						H2 2025 dates will be known at the end of March

Important notes:

Dates are GDS submission deadlines.

Several TSMC shuttles are extremely loaded. For any technology, please make your design registration as early as possible. We will work with you and do our best to get your design on the run. If required, a waiting list will be created.

Bumping is available upon request for all 12-inch technologies.

Contact eptsmc@imec.be if any of the following options are used: Bumping, MTP/OTP.

Prices for TSMC technologies can be calculated through the online Price Request Form:

Exceptionally, prices for the TSMC University FinFET Program can be found here:

When 4 or more independent sub-designs are registered in one MPW submission to optimise the minimum charged area, an additional verification charge of 1,000 USD is applicable. This is regardless of the request and charges for sub die sawing (6 USD per additional die obtained from the base MPW submission).

TSMC mini@sic	Jan	Feb	Mar	Apr	Jun	Aug	Sep	Oct	Nov
TSMC 0.13µm CMOS BCD plus				30				29
TSMC 65nm CMOS Low Power MS/RF		19		16	18		24		12
TSMC 65nm CMOS GP MS/RF			26					15
TSMC 40nm CMOS Low Power MS/RF			26				17
TSMC 28nm CMOS RF HPC+	29			16	25	27		22
TSMC 16nm CMOS RF FinFET Compact			26						19

Important notes:

Dates are GDS submission deadlines.

Please check additional technology options for TSMC mini@sic:

Please check additional technology options for the TSMC University FinFET Program:

TSMC mini@sic Pricelist	Standard prices		Discounted prices
	EUR / min area	EUR / extra area	EUR / min area	EUR / extra area
TSMC 130 BCD+ (min area = 6 mm²)	14,054	232 / 0.1 mm²	12,554	191 / 0.1 mm²
TSMC 65 LP/GP MS RF (min area = 1 mm²)	4,491	419 / 0.1 mm²	3,691	360 / 0.1 mm²
TSMC 40 LP MS RF (min area = 3 mm²) ¹	21,386	664 / 0.1 mm²	18,386	602 / 0.1 mm²
TSMC 28 HPC+ RF (min area = 1 mm²) ¹	10,609	919 / 0.1 mm²	8,509	834 / 0.1 mm²
TSMC 16 FFC RF (min area = 1mm²) ^{2, 3}	30,592	2,827 / 0.1 mm²	26,592	2,568 / 0.1 mm²

Important notes:

The prices are area based, and the aspect ratio is free to choose but it is strongly recommended not to have sides less than 1mm.
Subdicing is not supported on mini@sic.
Design registration must be done at least 3 months in advance, preferably at the moment of reservation.

¹ The areas in the table for 28nm and 40nm are on-silicon dimensions. This means the designed area can be (area/0.81).

²The areas in the table for 16nm indicates on-silicon dimensions. This means the designed area can be (area/0.9604).

Please check additional technology options for TSMC mini@sic:

³ Prices and technology options for the TSMC University FinFET Program can be found here:

UMC MPW	Feb	Mar	Apr	May	Jun	Aug	Sep	Nov	Dec
UMC 28N Logic/Mixed-Mode – HPC	3			12		4		10
UMC 40N Logic/Mixed-Mode – LP	17	31				4			1
UMC 65N Logic/Mixed-Mode/RF – LL			14		30		29
UMC L110AE Logic/Mixed-Mode/RF		31			2		1
UMC L180 Logic GII, Mixed-Mode/RF			7				29

Important notes: Dates are GDS submission deadlines. Design registration must be done at least 3 weeks in advance.

Additional technology options are available:

UMC MPW Pricelist	Standard EUR / block	Discounted EUR / block
UMC L180 Logic GII, Mixed-Mode/RF	19,000 ¹	18,060 ¹
UMC L110AE Logic/Mixed-Mode/RF	34,800 ¹	33,060¹
UMC L65nm Logic, Mixed-Mode/ RF – LL/SP	50,600 ²	48,080 ²
UMC 40N Logic/Mixed-Mode – LP	98,050 ²	93,160 ²
UMC 28N Logic/ Mixed-Mode – HPC	On request. Please, contact epumc@imec.be

Important notes:

¹ Price = per block of 5mm x 5mm needed to fit the design in.
² Price = per block of 4mm x 4mm needed to fit the design in.

UMC mini@sic		Jan	Feb	Mar	Apr	May	Jun	Jul	Aug	Sep	Oct	Nov	Dec
UMC L180 Mixed-Mode/RF				31						22

Important notes: Dates are GDS submission deadlines. Design registration must be done at least 3 weeks in advance.

Additional technology options are available:

UMC mini@sic Pricelist		Standard EUR / block	Discounted EUR / block
UMC L180 Mixed-Mode/RF – 1P6M – 1.8V/3.3V *		4,110 ¹	3,430 ¹

Important notes:

¹ Price = per block of 1525μm x 1525μm needed to fit the design in. Adding two blocks together to one block is possible.

* UMC 0.18μm mini@sic rules

When the standard block of 5mm x 5mm is divided into 9 regular square sub-blocks, customers participating in the mini@sic program can submit one sub-block or multiple sub-blocks, depending on the size of their design:

single sub-block: design may not be larger than 1525μm x 1525μm
2 sub-blocks: design may not be larger than 3240μm x 1525μm
3 sub-blocks: design may not be larger than 4960μm x 1525μm
4 sub-blocks: design may not be larger than 3240μm x 3240μm
6 sub-blocks: design may not be larger than 4960μm x 3240μm

Final price = number of sub-blocks needed to fit in the design * sub-block price.

imec MPW	Jan	Mar	Jun	Sep
imec Si-Photonics Passives+			4
imec Si-Photonics iSiPP50G		12		17
imec GaN-IC on SOI 100V	Coming soon
GaN-IC on SOI 650V	Coming soon

Important notes: Dates indicate deadlines for submission of the first version of the GDS file.
Design registration should be done at least 4 weeks in advance.

Admin. procedure must be finished at least 1 week before the dates indicated in the table.

imec MPW Pricelist Si-Photonics Passives+ ^{1, 2}	Standard EUR	Discounted EUR
Half block – horizontal (5.15mm x 2.5mm) or vertical (2.5mm x 5.15mm)	6,700	6,400
1 block (5.15mm x 5.15mm)	12,800	12,100
2 blocks – horizontal (10.45mm x 5.15mm) or vertical (5.15mm x 10.45mm)	22,700	21,500
4 blocks (10.45mm x 10.45mm)	44,000	42,000
Larger sizes	Please, contact epsiphot@imec.be
Extra Options
Extra set of half block chips (10 samples)	+2,500	+2,200
Extra set of chips (1 block or larger; 20 samples)	+2,500	+2,200
Si-Photonics iSiPP50G ^{1, 2}
Quarter block (2.5mm x 2.5mm)	11,000	10,500
Half block – horizontal (5.15mm x 2.5mm) or vertical (2.5mm x 5.15mm)	22,000	21,000
1 block (5.15mm x 5.15mm)	44,000	42,000
2 blocks – horizontal (10.45mm x 5.15mm) or vertical (5.15mm x 10.45mm)	88,000	83,500
4 blocks (10.45mm x 10.45mm)	165,000	157,000
Larger sizes	Please, contact epsiphot@imec.be
Extra Options
Extra set of quarter block chips (10 samples)	+2,500	+2,200
Extra set of half block chips (10 samples)	+2,500	+2,200
Extra set of chips (1 block or larger; 20 samples)	+2,500	+2,200

Important notes:

¹ There is a new process for the waveguides. Existing users, please be cautious.

² Number of prototypes in standard order depends on design size: 20 for 1 block or larger, 10 for half block or smaller.
Because of typical MPW logistics, we may sometimes deliver more chips than ordered.

imec MPW Pricelist GaN-IC on SOI 200V and 650V	Standard EUR	Discounted EUR
Half block (2.5mm x 5.18mm) *	22,000	20,240
Standard block (5.18mm x 5.18mm)	44,000	40,480
Double block (10.54mm x 5.18mm)	88,000	80,960
Extra Options
Extra set of chips (40 samples)	+5,000	+5,000
Sub-dicing **	+1,000	+1,000

Important notes: Regular number of samples is 40 .
Due to the nature of MPW logistics, more chips than ordered may sometimes be shipped.
* This option is only available to academic institutions.

** Per additional dicing lane, following MPW templates only. Sub-dicing options must be approved by the technical team. Please contact ganmpw@imec-int.com in advance to evaluate your request.

Pragmatic MPW		Jan	Feb	Mar	Apr	May	Jun	Jul	Aug	Sep	Oct	Nov	Dec
Helvellyn				3

Important notes:

The calendar for more MPW runs in 2025 will be published soon.

Dates indicate deadlines for submission of the first version of the GDS file. Design registration should be done at least 4 weeks in advance.

Full-wafer runs are possible on demand. Please contact flexicmpw@imec-int.com.

Pragmatic MPW Pricelist	Standard EUR / mm²	Discounted EUR / mm²
FlexIC Helvellyn ^{1, 2}	700	600
Extra Options
Additional set of 50 dies ³	500	500

Important notes:

¹ Price = area (mm²) * price/mm². Delivery quantity = 50 dies in gel-box.

² Minimum die size is 3mm x 3mm. Larger die sizes and other dimensions are also possible, but please first contact flexicmpw@imec-int.com before registration.

³Maximum 9 additional sets (450 additional dies) can be ordered. For more dies, please first contact flexicmpw@imec-int.com before registration.

For the full-wafer run pricelist, please contact flexicmpw@imec-int.com.

SINTEF PiezoMEMS		Jan	Feb	Mar	Apr	May	Jun	Jul	Aug	Sep	Oct	Nov	Dec
SINTEF PiezoMEMS				17						15

Important notes:

Dates indicate deadlines for submission of the first version of the GDS file. Design registration should be done at least 4 weeks in advance.

SINTEF MPB Pricelist		Standard EUR	Discounted EUR
12 wafers		114,500	109,000
3 wafers		52,000	50,00

Important notes:

Additional services, such as dicing, are available on request.

News & Events

Schedules and Prices

SCHEDULES & PRICES

2024

2025 RUN SCHEDULES AND PRICES

DISCOUNTED PRICE

STANDARD PRICE