IHP offers standard 0.13μm and 0.25μm CMOS processes which provide NMOS, PMOS, isolated NMOS, and passive components, such as poly resistors and MIM capacitors. In addition to the standard CMOS processes, different front-end-of-line options are offered.
In 0.25μm CMOS, the standard backend offers 3 thin metal layers and two TopMetal layers (TopMetal1: fourth 2μm thick metal layer, TopMetal2: fifth 3μm thick metal layer). The backend for 0.13μm process offers 5 thin and 2 thick metal layers (TM1: 2 μm, TM2: 3 μm). Together with a high dielectric stack this enables increased performance of the passive RF components.
Technologies with an enhanced BEOL option with copper are offered.
SG13S is a high-performance 0.13 µm BiCMOS with npn-HBTs up to fT / fmax= 250/340 GHz, with 3.3 V I/O CMOS and 1.2 V logic CMOS.
SG13G2 is a 0.13 µm BiCMOS technology with much higher bipolar performance of fT/fmax = 350/450 GHz.
FEOL process SG13S together with 8 layer Cu BEOL option from X-FAB containing 4 thin Cu layers, 2 thick 3 µm Cu layers, a thin Al layer with 2 fF/µm MIM capacitor and a 2.8 µm Al top layer.
FEOL process SG13G2 together with 8 layer Cu BEOL option from X-FAB containing 4 thin Cu layers, 2 thick 3 µm Cu layers, a thin Al layer with 2 fF/µm MIM capacitor and a 2.8 µm Al top layer.
Thi is a monolithic photonic BiCMOS technology combining 0.25 µm CMOS, high-performance npn HBTs (fT / fmax = 220/290 GHz), and full photonic device set for C/O-band.
SG25H3 is a 0.25 µm technology with a set of npn-HBTs ranging from a higher RF performance (fT/fmax= 110/180 GHz) to higher breakdown voltages up to 7 V.
THis is a cost-effective technology with a set of npn-HBTs up to a breakdown voltage of 7 V.
The backend offers 3 (SG13: 5) thin and 2 thick metal layers (TM1: 2 μm, TM2: 3 μm).
A cadence-based mixed signal design kit is available. For high frequency designs an analogue Design Kit in ADS can be used. IHP’s reusable blocks and IPs for wireless and broadband are offered to support your designs.
MEMRES is a fully CMOS integrated memristive module based on resistive TiN / HfO2-x / TiN switching devices in SG13S technology, along with a Process Design Kit including layout and VerilogA simulation model.
The Localized Backside Etching module is offered to remove silicon locally to improve passive properties (available in all technologies).
PIC includes additional photonic design layers along with BiCMOS BEOL layers on SOI wafers.
TSV (Through Silicon Via) module is an additional option in SG13S and SG13G2 technologies that provides RF grounding by vias through silicon to improve RF performance.
Bumping for Flip Chip assembling bumps (Ni/Au, Ball size 80 μm).
Customers usually receive 40 diced samples and E-test data, including RF measurements. Exceptions are designs using EPIC technology, PIC and TSV module. In this case, only 25 samples will be delivered by default. Original wafer thickness is 750μm. After backlapping, standard samples thicknesses of 200μm and 300μm are available without additional costs.
Other backlapping options are available upon request.
An Engineering Run consists of a separate mask set and the delivery of 6 wafers. Additional wafers can be purchased upon request.