SCHEDULES & PRICES

2024

Schedules 2024

GENERAL MPW & MINI@SIC SCHEDULES - 2024

Here you can find General MPW and mini@sic run schedules and pricelists for 2024.

To reserve your seat on a run, please register your design in the Registration Form or contact the EUROPRACTICE partner responsible for the technology.

PRICELISTS - 2024

There are two prices in the EUROPRACTICE lists: Discounted and Standard.

 
DISCOUNTED PRICE

Three conditions should be met for Discounted prices:

  • Customer is an academic institution or a research facility from one of the 27 EU countries together with Albania, Armenia, Azerbaijan, Bosnia-Herzegovina, Georgia, Iceland, Israel, Liechtenstein, North Macedonia, Moldova, Montenegro, Norway, Switzerland, Turkey, Serbia, the UK and Ukraine.
  • Customer is a registered EUROPRACTICE member who has paid the Full-IC annual membership fee.
  • The intended design will be done for educational purposes or for publicly funded research.
 
STANDARD PRICE

Standard prices apply to all other customers.

ams OSRAM MPW
Jan
Feb
Mar
Apr
May
Jun
Jul
Aug
Sep
Oct
Nov
Dec
ams OSRAM 0.35µ CMOS C35B4C3 4M/2P/HR/5V IO
26
15
4
ams OSRAM 0.35µ CMOS C35OPTO 4M/2P/5V
26
15
4
ams OSRAM 0.35µ HV CMOS H35B4D3 120V 4M
13*
25*
ams OSRAM 0.35µ SiGe-BiCMOS S35D4M5 /
CMOS-RF C35B4M3 4M/4P Thick MET4 – MIM
7**
ams OSRAM 0.18µ CMOS atC18C6SH 6M/1P/HR/MIM/TW (Triple-well), 1.8V/3.3V
29
21

Important notes: Dates are GDS submission deadlines. Design registration must be done at least 2 weeks in advance.

*  MPW run on request

** Last offered MPW run

Fraunhofer IISB
Jan
Feb
Mar
Apr
May
Jun
Jul
Aug
Sep
Oct
Nov
Dec
4H-SiC CMOS HIGH TEMPERATURE
9

Important notes: Dates are GDS submission deadlines. Design registration must be done at least 4 weeks in advance.

The first design submission (for our review and feedback) must be done on 12 January 2024.

GLOBALFOUNDRIES MPW
Jan
Feb
Mar
Apr
May
Jun
Jul
Aug
Sep
Oct
Nov
Dec
GLOBALFOUNDRIES SiGe 8XP
19
18
10
8
GLOBALFOUNDRIES 130nm BCDlite – Gen2
11
9
GLOBALFOUNDRIES 55 nm BCDlite
25
25
17
GLOBALFOUNDRIES 45RFE
13
13
GLOBALFOUNDRIES 45nm SPCLO – Silicon Photonics
14
3
GLOBALFOUNDRIES 28 nm SLPe
25
7
GLOBALFOUNDRIES 22 nm FDSOI
8
26
15
10
29
23
15
GLOBALFOUNDRIES 12 nm LP+
10
14

Important notes: Dates are Registration deadlines after which designs cannot be accepted.

Final GDSII file must be submitted within 6 weeks after this date.

Dates in red are preliminary.

cancellation fee is applicable if the registration is cancelled later than 2 weeks after the Registration deadline or if the customer is unable to provide a DRC-clean GDS before the Tapeout deadline.

IHP MPW
Jan
Feb
Mar
Apr
May
Jun
Jul
Aug
Sep
Oct
Nov
Dec
IHP SG13C SiGe:C RF CMOS
10
19
22
IHP SG13G2 SiGe:C Bipolar/Analog
10
19
22
IHP SG13G2Cu (FEOL process SG13G2 + Cu BEOL option from X-FAB)
1
19
22
IHP SG13G3Cu (FEOL process + Cu BEOL option from X-FAB)
19
22
IHP SG13G3 (FEOL process SG13G3Cu + Al-BEOL option)*
19
22
IHP SG13S SiGe:C Bipolar/Analog
10
19
22
IHP SG13SCu (FEOL process SG13S + Cu BEOL option from X-FAB)
1
19
22
IHP MEMRES for SG13S
10
22
IHP SG25 PIC (Photonics, Ge Photo-diode, BEOL)
26
IHP SG25H5_EPIC high performance BiCMOS + Photonic
18
IHP BEOL SG13 (M1 and Metal Layers Above) + optional LBE or TSV or RDL
9

Important notes: Dates are Registration deadlines. Final GDSII file must be submitted within 10 days after this date.

* For research and prototyping purposes only.

 

MEMRES is available for IHP SG13S technology with extra charge.

TSV and RDL are available for IHP SG13S and SG13G2 technologies with extra charge.

Cu Pillar and Bumping are available for all IHP technologies with extra charge; SG13C on request.

Local Backside Etching (LBE) is not offered for EPIC runs and runs with Cu-BEOL.

 
 
STMicroelectronics MPW
Jan
Feb
Mar
Apr
May
Jun
Jul
Aug
Sep
Oct
Nov
Dec
ST 28nm CMOS28FDSOI
1
ST 28nm CMOSP28FDSOI
24
ST 55nm BiCMOS055X
5
4
ST 65nm CMOS065
1*
ST 130nm BiCMOS9MW
2
ST 130nm HCMOS9A
2
4
ST 130nm SOI H9SOI-FEM
2*
ST 0.16µm BCD8sP
20
2
ST 0.16µm BCD8s-SOI
1*

Important notes: Dates are GDS submission deadlines. Design registration has to be done at least 4 weeks in advance.

* MPW run on request. Please contact cime-prototypage@grenoble-inp.fr  

Dates in red are preliminary.

TSMC MPW
Jan
Feb
Mar
Apr
May
Jun
Jul
Aug
Sep
Oct
Nov
Dec
TSMC 0.13µm CMOS BCD plus (12-inch)
17
8
24
6
TSMC 0.13µm CMOS Logic or MS/RF, GP or LP (12-inch)
17
8
24
6
TSMC 90nm CMOS Logic or MS/RF, GP or LP
6
12
7
4
TSMC 65nm CMOS Logic or MS/RF, GP or LP
7
27
22
26
18
20
TSMC 40nm CMOS Logic or MS/RF, LP
(no triple gate oxide)
7
21
27
24
29
24
28
25
23
20
TSMC 40nm CMOS Logic or MS/RF, GP
(no triple gate oxide)
21
24
28
23
TSMC 28nm CMOS Logic or RF HPC/HPC+
3
7
28
1
29
31
4
30
27
TSMC 22nm CMOS Logic or RF ULL
21
27
24
26
21
2
23
TSMC 16nm CMOS Logic or RF FinFET Compact
7
3
22
24
18
27
TSMC 7nm CMOS Logic or RF FinFET
3
3
2

Important notes:

Dates are GDS submission deadlines.

Several TSMC shuttles are extremely loaded. For any technology, please make your design registration as early as possible. We will work with you and do our best to get your design on the run. If required, a waiting list will be created.

 

The TSMC run schedule for the second half of 2024 will be published later this year. We will share it with you as soon as it is available.

 

Bumping is available upon request for all 12-inch technologies.

Contact eptsmc@imec.be if any of the following options are used: Bumping, MTP/OTP, Deep Trench, High Linearity MiM, Schottky Barrier Diode, ULL N/PMOS.

UMC MPW
Jan
Feb
Mar
Apr
May
Jun
Jul
Aug
Sep
Oct
Nov
Dec
UMC 28N Logic/Mixed-Mode – HPC
19
22
22
26
30
28
UMC 40N Logic/Mixed-Mode – LP
11
24
29
26
18
UMC 65N Logic/Mixed-Mode/RF – LL
2
26
2
21
UMC L110AE Logic/Mixed-Mode/RF
26
3
2
25
UMC L180 Logic GII, Mixed-Mode/RF
4
26

Important notes: Dates are GDS submission deadlines. Design registration must be done at least 3 weeks in advance.

 

Additional technology options are available:

UMS
Jan
Feb
Mar
Apr
May
Jun
Jul
Aug
Sep
Oct
Nov
Dec
UMS GH25|GaN HEMT
22
20
UMS GH15|GaN HEMT
24
22
UMS PH10|GaAs pHEMT
19
13

Important notes: Dates are GDS submission deadlines. Design registration must be done at least 4 weeks in advance.

UMS may postpone the run depends on the cummalative chip area. At the area less than 10 mm² the run will be started in consultation with UMS. Wafer size: 4″

X-FAB MPW
Jan
Feb
Mar
Apr
May
Jun
Jul
Aug
Sep
Oct
Nov
Dec
XT011 0.11µ HV SOI CMOS
11
6
26
18
XR013 0.13µ RF SOI CMOS *
12
12
XR013 0.13µ XIPD
13
4
XH018 0.18µ HV NVM CMOS E-FLASH
5
25
24
7
XP018 0.18µ NVM CMOS *
29
27
16
XT018 0.18µ HV SOI CMOS
26
22
12
4
XS018 0.18µ OPTO *
5
8
XH035 0.35µ HV CMOS
4
5
4
XMB10 MEMS
16

Important notes: Dates are GDS submission deadlines. Registration should be done at least 2 weeks in advance.

* In case of cancellation, there is a possibility to order these technologies by MLM.

 

Please take a look at additional technology options:

AMF MPW
Jan
Feb
Mar
Apr
May
Jun
Jul
Aug
Sep
Oct
Nov
Dec
Si-Photonics fabrication process AMF
20
14

Important notes: For registration, please contact cime-prototypage@grenoble-inp.fr

CORNERSTONE MPW
Jan
Feb
Mar
Apr
May
Jun
Jul
Aug
Sep
Oct
Nov
Dec
CORNERSTONE Si-Photonics: 220 nm SOI passives
21
29
27
CORNERSTONE Si-Photonics: 220 nm SOI actives
26
CORNERSTONE Si-Photonics: 340 nm SOI passives
27
25
CORNERSTONE Si-Photonics: 500 nm SOI passives
28
CORNERSTONE SiN-Photonics
3
24
18
CORNERSTONE Si-Photonics: Suspended-Si
24
23
CORNERSTONE Ge-on-Si
24
23

Important notes: Dates are GDS submission deadlines. Registration should be done at least 4 weeks in advance.

Graphenea MPW
Jan
Feb
Mar
Apr
May
Jun
Jul
Aug
Sep
Oct
Nov
Dec
Graphenea Process Flow 1 – General
7
7
Graphenea Process Flow 2 – Biosensing
3
2
Graphenea Process Flow 3 – HKMG
5
4

Important notes: Dates indicate deadlines for submission of the first version of the GDS file.
Design registration should be done at least 4 weeks in advance.

imec MPW
Jan
Feb
Mar
Apr
May
Jun
Jul
Aug
Sep
Oct
Nov
Dec
imec Si-Photonics Passives+
5
imec Si-Photonics iSiPP50G
20
18
imec GaN-IC on SOI 200V
22
GaN-IC on SOI 650V
18

Important notes: Dates indicate deadlines for submission of the first version of the GDS file.
Design registration should be done at least 4 weeks in advance.

Admin. procedure must be finished at least 1 week before the dates indicated in the table.

LioniX MPW
Jan
Feb
Mar
Apr
May
Jun
Jul
Aug
Sep
Oct
Nov
Dec
LNX SiN-Photonics TriPleX VIS
31
15
LNX SiN-Photonics TriPleX 1550
31
31
15
LNX SiN-Photonics TriPleX 850
15
29

Important notes:

Dates are GDS submission deadlines. For registration dates and other details, please contact marc.rensing@tyndall.ie

TBD * – The exact dates in June for TriPleX VIS and in September for TriPleX 850 are to be defined.

Pragmatic MPW
Jan
Feb
Mar
Apr
May
Jun
Jul
Aug
Sep
Oct
Nov
Dec
Helvellyn
6
22
25

Important notes:

Dates indicate deadlines for submission of the first version of the GDS file. Design registration should be done at least 4 weeks in advance.

Full-wafer runs are possible on demand. Please contact flexicmpw@imec-int.com.

Science MPW
Jan
Feb
Mar
Apr
May
Jun
Jul
Aug
Sep
Oct
Nov
Dec
PolyMUMPs
20
SOIMUMPS
27
2
29
PiezoMUMPS
16
14
10

Important notes: Dates indicate deadlines for both Registration and submission of the first version of the GDS file.