SCHEDULES & PRICES

2024

Schedules 2024

GENERAL MPW & MINI@SIC SCHEDULES - 2024

Here you can find General MPW and mini@sic run schedules and pricelists for 2024.

To reserve your seat on a run, please register your design in the Registration Form or contact the EUROPRACTICE partner responsible for the technology.

PRICELISTS - 2024

There are two prices in the EUROPRACTICE lists: Discounted and Standard.

DISCOUNTED PRICE

Three conditions should be met for Discounted prices:

Customer is an academic institution or a research facility from one of the 27 EU countries together with Albania, Armenia, Azerbaijan, Bosnia-Herzegovina, Georgia, Iceland, Israel, Liechtenstein, North Macedonia, Moldova, Montenegro, Norway, Switzerland, Turkey, Serbia, the UK and Ukraine.
Customer is a registered EUROPRACTICE member who has paid the Full-IC annual membership fee.
The intended design will be done for educational purposes or for publicly funded research.

STANDARD PRICE

Standard prices apply to all other customers.

GLOBALFOUNDRIES MPW	Jan	Feb	Mar	Apr	May	Jun	Jul	Aug	Sep	Nov	Dec
GLOBALFOUNDRIES SiGe 8XP			19			18			10		8
GLOBALFOUNDRIES 130nm BCDlite – Gen2			11						9
GLOBALFOUNDRIES 55 nm BCDlite			25			25			24		25
GLOBALFOUNDRIES 45RFE		13						13
GLOBALFOUNDRIES 45nm SPCLO – Silicon Photonics				9				13			10
GLOBALFOUNDRIES 28 nm SLPe		26			20				20	25
GLOBALFOUNDRIES 22 nm FDSOI	8	26		15		10	29		23	15
GLOBALFOUNDRIES 12 nm LP+	10							14

Important notes: Dates are Registration deadlines after which designs cannot be accepted.

Final GDSII file must be submitted within 6 weeks after this date.

Dates in red are preliminary.

A cancellation fee is applicable if the registration is cancelled later than 2 weeks after the Registration deadline or if the customer is unable to provide a DRC-clean GDS before the Tapeout deadline.

GLOBALFOUNDRIES MPW Pricelist	Standard EUR / mm²	Discounted EUR / mm²
GLOBALFOUNDRIES SiGe 8XP	4,700 ¹	4,500 ¹
GLOBALFOUNDRIES 130 nm BCDlite	1,900 ²	1,800 ²
GLOBALFOUNDRIES 55 nm BCDlite	5,500 ¹	5,200 ¹
GLOBALFOUNDRIES 45RFE	10,200 ¹	9,800¹
GLOBALFOUNDRIES 45nm SPCLO -Silicon Photonics (price per fixed block 5mm x 5mm)	231,000	220,000
GLOBALFOUNDRIES 28 nm SLPe	12,100 ³	11,500 ³
GLOBALFOUNDRIES 22 nm FDSOI	17,900 ³	17,000 ³
GLOBALFOUNDRIES 12 nm LP+	29,400 ³	28,000 ³

Important notes:

¹ Price = area (mm²) * price/mm² with min. fabrication cost equivalent to 12 mm². Any edge length between 1.0 mm to 11 mm is possible.

The mentioned die size is referred to the Pre-Shrink die size.

² Price = area (mm²) * price/mm² with min. fabrication cost equivalent to 25 mm². Any edge length between 1.0 mm to 11 mm is possible.

The mentioned die size is referred to the Pre-Shrink die size.

³ Price = area (mm²) * price/mm² with min. fabrication cost equivalent to 9 mm². Any edge length between 1.0 mm to 11 mm is possible.

The mentioned die size is referred to the Pre-Shrink die size.

GLOBALFOUNDRIES mini@sic	Jan	Feb	Mar	Apr	May	Jun	Jul	Aug	Sep	Nov	Dec
GLOBALFOUNDRIES SiGe 8XP			19			18			10		8
GLOBALFOUNDRIES 130nm BCDlite – Gen2			11						9
GLOBALFOUNDRIES 55 nm BCDlite			25			25			24		25
GLOBALFOUNDRIES 45RFE		13						13
GLOBALFOUNDRIES 45nm SPCLO – Silicon Photonics				9				13			10
GLOBALFOUNDRIES 28 nm SLPe		26			20				20	25
GLOBALFOUNDRIES 22 nm FDSOI	8	26		15		10	29		23	15
GLOBALFOUNDRIES 12 nm LP+	10							14

Important notes: The mini@sic model of GlobalFoundries is available only for universities and research institutes.

Dates are Registration deadlines after which designs cannot be accepted.

Final GDSII file must be submitted within 6 weeks after this date.

Dates in red are preliminary.

GLOBALFOUNDRIES mini@sic Pricelist	Standard EUR / mm²	Discounted EUR / mm²
GLOBALFOUNDRIES SiGe 8XP	7,400 ¹	7,000 ¹
GLOBALFOUNDRIES 130nm BCDlite – Gen2	3,200 ²	3,000 ²
GLOBALFOUNDRIES 55 nm BCDlite	8,100 ¹	7,700 ¹
GLOBALFOUNDRIES 45RFE	12,800³	12,200 ³
GLOBALFOUNDRIES 45nm SPCLO -Silicon Photonics	147,000 ⁴	140,000 ⁴
GLOBALFOUNDRIES 28 nm SLPe	16,700 ³	15,900 ³
GLOBALFOUNDRIES 22 nm FDSOI	23,600 ³	22,500 ³
GLOBALFOUNDRIES 12 nm LP+	36,800 ³	35,000 ³

Important notes:

¹ Price = area (mm²) * price/mm² with min. fabrication cost equivalent to 2 mm². The mentioned die size is referred to the Pre-Shrink die size.

² Price = area (mm²) * price/mm² with min. fabrication cost equivalent to 4 mm². The mentioned die size is referred to the Pre-Shrink die size.

³ Price = area (mm²) * price/mm² with min. fabrication cost equivalent to 1 mm².The mentioned die size is referred to the Pre-Shrink die size.

⁴ Price = fixed block size of 5mm x 2.455mm or 2.455mm x 5mm.

TSMC MPW	Jan	Feb	Mar	Apr	May	Jun
TSMC 0.13µm CMOS BCD plus (12-inch)	17				8
TSMC 0.13µm CMOS Logic or MS/RF, GP or LP (12-inch)	17				8
TSMC 90nm CMOS Logic or MS/RF, GP or LP			6			12
TSMC 65nm CMOS Logic or MS/RF, GP or LP		7	27		22
TSMC 40nm CMOS Logic or MS/RF, GP or LP (no triple gate oxide)		7 21	27	24	29
TSMC 28nm CMOS Logic or RF HPC/HPC+	3	7 28			1 29
TSMC 16nm CMOS Logic or RF FinFET Compact		7		3	22
TSMC 7nm CMOS Logic FinFET	3			3

Important notes:

Dates are GDS submission deadlines.

Several TSMC shuttles are extremely loaded. For any technology, please make your design registration as early as possible. We will work with you and do our best to get your design on the run. If required, a waiting list will be created.

The TSMC run schedule for the second half of 2024 will be published later this year. We will share it with you as soon as it is available.

Bumping is available upon request for all 12-inch technologies.

Contact eptsmc@imec.be if any of the following options are used: Bumping, MTP/OTP, Deep Trench, High Linearity MiM, Schottky Barrier Diode, ULL N/PMOS.

Prices for TSMC technologies can be calculated through the online Price Request Form:

Exceptionally, prices for the TSMC University FinFET Program can be found here:

When 4 or more independent sub-designs are registered in one MPW submission to optimise the minimum charged area, an additional verification charge of 1,000 USD is applicable. This is regardless of the request and charges for sub die sawing (6 USD per additional die obtained from the base MPW submission).

TSMC mini@sic	Jan	Feb	Mar	Apr	May
TSMC 0.13µm CMOS BCD plus					1
TSMC 65nm CMOS Low Power MS/RF		21		17
TSMC 40nm CMOS Low Power MS/RF	31
TSMC 28nm CMOS RF HPC+	31			24
TSMC 16nm CMOS RF FinFET Compact			27

Important notes:

Dates are GDS submission deadlines.

Please check additional technology options for TSMC mini@sic:

Please check additional technology options for the TSMC University FinFET Program:

TSMC mini@sic Pricelist	Standard prices		Discounted prices
	EUR / min area	EUR / extra area	EUR / min area	EUR / extra area
TSMC 130 BCD+ (min area = 6 mm²)	13,982	231 / 0.1 mm²	12,482	190 / 0.1 mm²
TSMC 65 LP MS RF (min area = 1 mm²)	4,462	418 / 0.1 mm²	3,662	358 / 0.1 mm²
TSMC 40 LP MS RF (min area = 3 mm²) ¹	21,249	662 / 0.1 mm²	18,249	599 / 0.1 mm²
TSMC 28 HPC+ RF (min area = 1 mm²) ¹	10,541	915 / 0.1 mm²	8,441	830 / 0.1 mm²
TSMC 16 FFC RF (min area = 1mm²) ^{2, 3}	30,364	2,814 / 0.1 mm²	26,364	2,557 / 0.1 mm²

Important notes:

The prices are area based, and the aspect ratio is free to choose but it is strongly recommended not to have sides less than 1mm.
Subdicing is not supported on mini@sic.
Design registration must be done at least 3 months in advance, preferably at the moment of reservation.

¹ The areas in the table for 28nm and 40nm are on-silicon dimensions. This means the designed area can be (area/0.81).

²The areas in the table for 16nm indicates on-silicon dimensions. This means the designed area can be (area/0.9604).

Please check additional technology options for TSMC mini@sic:

³ Prices and technology options for the TSMC University FinFET Program can be found here:

UMC MPW	Jan	Feb	Mar	Apr	Jun	Jul	Aug	Sep	Oct	Nov
UMC 28N Logic/Mixed-Mode – HPC		19		22		22	26		28
UMC 40N Logic/Mixed-Mode – LP			11		24	29	26			18
UMC 65N Logic/Mixed-Mode/RF – LL	2	26		22				2	21
UMC L110AE Logic/Mixed-Mode/RF		26		29		1		2	28
UMC L180 Logic GII, Mixed-Mode/RF			4			8		30

Important notes: Dates are GDS submission deadlines. Design registration must be done at least 3 weeks in advance.

Additional technology options are available:

UMC MPW Pricelist	Standard EUR / block	Discounted EUR / block
UMC L180 Logic GII, Mixed-Mode/RF	19,000 ¹	18,060 ¹
UMC L110AE Logic/Mixed-Mode/RF	34,800 ¹	33,060¹
UMC L65nm Logic, Mixed-Mode/ RF – LL/SP	50,600 ²	48,080 ²
UMC 55N Logic/Mixed-Mode/RF – SP	45,425 ²	43,171 ²
UMC 40N Logic/Mixed-Mode – LP	98,050 ²	93,160 ²
UMC 28N Logic/ Mixed-Mode – HPC	On request. Please, contact epumc@imec.be

Important notes:

¹ Price = per block of 5mm x 5mm needed to fit the design in.
² Price = per block of 4mm x 4mm needed to fit the design in.

UMC mini@sic	Feb	Mar	Apr	Jul	Aug	Sep	Oct
UMC 65N Logic/Mixed-Mode/RF – LL	19		15		26		14
UMC L110AE Mixed-Mode/RF		4			26
UMC L180 Mixed-Mode/RF	26			1		23

Important notes: Dates are GDS submission deadlines. Design registration must be done at least 3 weeks in advance.

Additional technology options are available:

UMC mini@sic Pricelist	Standard EUR / block	Discounted EUR / block
UMC L180 Mixed-Mode/RF – 1P6M – 1.8V/3.3V *	4,110 ¹	3,430 ¹
UMC L110AE Logic/Mixed-Mode/RF **	8,920 ²	8,070 ²
UMC L65N Logic/Mixed-Mode LL ***	12,970 ³	11,720 ³

Important notes:

¹ Price = per block of 1525μm x 1525μm needed to fit the design in. Adding two blocks together to one block is possible.

² Price = per block of 2425μm x 1525μm needed to fit the design in.

³ Price = per block of 1875μm x 1875μm needed to fit the design in. Adding two blocks together to one block is possible.

* UMC 0.18μm mini@sic rules

When the standard block of 5mm x 5mm is divided into 9 regular square sub-blocks, customers participating in the mini@sic program can submit one sub-block or multiple sub-blocks, depending on the size of their design:

single sub-block: design may not be larger than 1525μm x 1525μm
2 sub-blocks: design may not be larger than 3240μm x 1525μm
3 sub-blocks: design may not be larger than 4960μm x 1525μm
4 sub-blocks: design may not be larger than 3240μm x 3240μm
6 sub-blocks: design may not be larger than 4960μm x 3240μm

Final price = number of sub-blocks needed to fit in the design * sub-block price.

** UMC 0.11μm mini@sic rules

single sub-block: design may not be larger than 2425μm x 1525μm
2 sub blocks: design may not be larger than 2425μm x 3140μm

*** UMC 65nm mini@sic rules

For the mini@sic program, customers can submit one sub-block or multiple sub-blocks, depending on the size of their design:

single sub-block: design may not be larger than 1875μm x 1875μm
2 sub-blocks: design may not be larger than 3950μm x 1875μm

imec MPW	Mar	Apr	Jun	Sep
imec Si-Photonics Passives+			5
imec Si-Photonics iSiPP50G	20			18
imec GaN-IC on SOI 200V		24
GaN-IC on SOI 650V				25

Important notes: Dates indicate deadlines for submission of the first version of the GDS file.
Design registration should be done at least 4 weeks in advance.

Admin. procedure must be finished at least 1 week before the dates indicated in the table.

imec MPW Pricelist Si-Photonics Passives+ ^{1, 2}	Standard EUR	Discounted EUR
Half block – horizontal (5.15mm x 2.5mm) or vertical (2.5mm x 5.15mm)	6,700	6,400
1 block (5.15mm x 5.15mm)	12,800	12,100
2 blocks – horizontal (10.45mm x 5.15mm) or vertical (5.15mm x 10.45mm)	22,700	21,500
4 blocks (10.45mm x 10.45mm)	44,000	42,000
Larger sizes	Please, contact epsiphot@imec.be
Extra Options
Extra set of half block chips (10 samples)	+2,500	+2,200
Extra set of chips (1 block or larger; 20 samples)	+2,500	+2,200
Si-Photonics iSiPP50G ^{1, 2}
Quarter block (2.5mm x 2.5mm)	11,000	10,500
Half block – horizontal (5.15mm x 2.5mm) or vertical (2.5mm x 5.15mm)	22,000	21,000
1 block (5.15mm x 5.15mm)	44,000	42,000
2 blocks – horizontal (10.45mm x 5.15mm) or vertical (5.15mm x 10.45mm)	88,000	83,500
4 blocks (10.45mm x 10.45mm)	165,000	157,000
Larger sizes	Please, contact epsiphot@imec.be
Extra Options
Extra set of quarter block chips (10 samples)	+2,500	+2,200
Extra set of half block chips (10 samples)	+2,500	+2,200
Extra set of chips (1 block or larger; 20 samples)	+2,500	+2,200

Important notes:

¹ There is a new process for the waveguides. Existing users, please be cautious.

² Number of prototypes in standard order depends on design size: 20 for 1 block or larger, 10 for half block or smaller.
Because of typical MPW logistics, we may sometimes deliver more chips than ordered.

imec MPW Pricelist GaN-IC on SOI 200V and 650V	Standard EUR	Discounted EUR
Half block (2.5mm x 5.18mm) *	22,000	20,240
Standard block (5.18mm x 5.18mm)	44,000	40,480
Double block (10.54mm x 5.18mm)	88,000	80,960
Extra Options
Extra set of chips (40 samples)	+5,000	+5,000
Sub-dicing **	+1,000	+1,000

Important notes: Regular number of samples is 40 .
Due to the nature of MPW logistics, more chips than ordered may sometimes be shipped.
* This option is only available to academic institutions.

** Per additional dicing lane, following MPW templates only. Sub-dicing options must be approved by the technical team. Please contact ganmpw@imec-int.com in advance to evaluate your request.

Science MPW	Jan	Feb	Mar	May	Jul	Sep	Oct
PolyMUMPs			20
SOIMUMPS		27			2		29
PiezoMUMPS	16			14		10

Important notes: Dates indicate deadlines for both Registration and submission of the first version of the GDS file.

Science MPW Pricelist		Standard EUR / block	Discounted EUR / block
PolyMUMPs (10mm x 10mm), SOIMUMPs (11 mm x 11mm), PiezoMUMPs (11mm x 11mm)		6,500	5000

News & Events

Schedules and Prices

SCHEDULES & PRICES

2024

GENERAL MPW & MINI@SIC SCHEDULES - 2024

PRICELISTS - 2024

DISCOUNTED PRICE

STANDARD PRICE