SCHEDULES & PRICES

2023

Schedules 2023

GENERAL MPW & MINI@SIC SCHEDULES - 2023

Here you can find General MPW and mini@sic run schedules and pricelists for 2023.

To reserve your seat on a run, please register your design in the Registration Form or contact the EUROPRACTICE partner responsible for the technology.

PRICELISTS - 2023

There are two prices in the EUROPRACTICE lists: Discounted and Standard.

 
DISCOUNTED PRICE

Three conditions should be met for Discounted prices:

  • Customer is an academic institution or a research facility from one of the 28 EU countries together with Albania, Armenia, Azerbaijan, Belarus, Bosnia-Herzegovina, Georgia, Iceland, Israel, Liechtenstein, North Macedonia, Moldova, Montenegro, Norway, Switzerland, Turkey, Serbia and Ukraine.
  • Customer is a registered EUROPRACTICE member who has paid the Full-IC annual membership fee.
  • The intended design will be done for educational purposes or for publicly funded research.
 
STANDARD PRICE

Standard prices apply to all other customers.

We are currently working on the Schedules and Prices 2023. We will post more information here as soon as it is available to us.

ams MPW
Jan
Feb
Mar
Apr
May
Jun
Jul
Aug
Sep
Oct
Nov
Dec
ams 0.35µ CMOS C35B4C3 4M/2P/HR/5V IO
27
17
6
ams 0.35µ CMOS C35OPTO 4M/2P/5V
27
17
6
ams 0.35µ HV CMOS H35B4D3 120V 4M
8
27
ams 0.35µ SiGe-BiCMOS S35D4M5 /
CMOS-RF C35B4M3 4M/4P Thick MET4 – MIM
9
ams 0.18µ CMOS atC18C6SH 6M/1P/HR/MIM/TW (Triple-well), 1.8V/3.3V
20

Important notes: Dates are GDS submission deadlines. Design registration must be done at least 2 weeks in advance.

Dates in red are MPW runs on request.

Fraunhofer IISB
Jan
Feb
Mar
Apr
May
Jun
Jul
Aug
Sep
Oct
Nov
Dec
4H-SiC CMOS HIGH TEMPERATURE
10
20

Important notes: Dates are GDS submission deadlines. Design registration must be done at least 4 weeks in advance.

Dates in red are preliminary.

GLOBALFOUNDRIES MPW
Jan
Feb
Mar
Apr
May
Jun
Jul
Aug
Sep
Oct
Nov
Dec
GLOBALFOUNDRIES SiGe 8XP
22
23
22
23
GLOBALFOUNDRIES 130nm BCDlite – Gen2
27
28
GLOBALFOUNDRIES 55 nm BCDlite
17
26
19
GLOBALFOUNDRIES 45RFSOI
11
9
1
GLOBALFOUNDRIES 45nm SPCLO – Silicon Photonics
15
13
12
12
GLOBALFOUNDRIES 28 nm SLPe
20
15
21
28
GLOBALFOUNDRIES 22 nm FDSOI
2
6
1
26
14
3
GLOBALFOUNDRIES 12 nm LP+
22
13

Important notes: Dates are Registration deadlines after which designs cannot be accepted.

Final GDSII file must be submitted within 6 weeks after this date.

Dates in red are preliminary.

cancellation fee is applicable if the registration is cancelled later than 2 weeks after the Registration deadline or if the customer is unable to provide a DRC-clean GDS before the Tapeout deadline.

IHP MPW
Jan
Feb
Mar
Apr
May
Jun
Jul
Aug
Sep
Oct
Nov
Dec
IHP SGB25V 0.25µ SiGe:C Bipolar/Analog, Ft/Fmax= 75/95GHz, 5M/MIM, breakdown voltages up to 7V
17
20**
IHP SG25H3 0.25µ SiGe:C Bipolar/Analog, Ft/Fmax= 110/180GHz, 5M/MIM, breakdown voltages up to 7V
17
SG25H5_EPIC Bipolar/Analog, Ft/Fmax= 220/290GHz, 7M/MIM + Photonics
13
20
IHP SG13S SiGe:C Bipolar/Analog, Ft/Fmax= 250/340GHz, 7M/MIM + optional TSV
16
1
24
IHP SG13C SiGe:C CMOS 7M/MIM
16
1
24
IHP SG13G2 SiGe:C Bipolar/Analog, Ft/Fmax= 350/450GHz, 7M/MIM + optional TSV
16
1
24
IHP SG13G2Cu FEOL process SG13G2 together with Cu BEOL option
10
16*
1
24
IHP SG13G3Cu SiGe:C Bipolar/Analog, Ft/Fmax= 500/700GHz FEOL process with Cu BEOL option
10
24
IHP SG13SCu FEOL process SG13S together with Cu BEOL option
10
16*
1
24
IHP SG13S + MEMRES Module + RDL
16
24
IHP SG13G2 + RDL
16
24
IHP SG25 PIC (Photonics, Ge Photo-diode, BEOL)
28
IHP BEOL SG13 (M1 and Metal Layers Above) + optional LBE or TSV or RDL
10

Important notes: Dates are Registration deadlines. Final GDSII file must be submitted within 10 days after this date.

 

* Additional MPW runs are offered only on request and when the cumulative area > 10 mm².

** Additional MPW runs are offered only on special request.

MEMRES is available for the IHP SG13S technology with extra charge.

 

TSV and RDL are available for IHP SG13S and SG13G2 technologies with extra charge.

Cu Pillar and Bumping are available for all IHP technologies with extra charge.

Local Backside Etching (LBE) is not offered for EPIC runs and runs with Cu-BEOL.

 
 
TSMC MPW
Jan
Feb
Mar
Apr
May
Jun
Jul
Aug
Sep
Oct
Nov
Dec
TSMC 0.13µm CMOS BCD plus (12-inch)
18
3
TSMC 0.13µm CMOS Logic or MS/RF, GP or LP (12-inch)
18
3
TSMC 90nm CMOS Logic or MS/RF, GP or LP
8
14
TSMC 65nm CMOS Logic or MS/RF, GP or LP
1
1
5
26
24
TSMC 40nm CMOS Logic or MS/RF, GP or LP (no triple gate oxide)
25
22
29
26
31
TSMC 28nm CMOS Logic or RF HPC/HPC+
1
1
3
31
TSMC 16nm CMOS Logic or RF FinFET Compact
25
29
24

Important notes:

Dates are GDS submission deadlines.

Several TSMC shuttles are extremely loaded. For any technology, please make your design registration as early as possible. We will work with you and do our best to get your design on the run. If required, a waiting list will be created.

 

The TSMC run schedule for the second half of 2023 will be published in late March. We will share it with you as soon as it is available.

Bumping is available upon request for all 12-inch technologies.

 

Contact eptsmc@imec.be if any of the following options are used: Bumping, MTP/OTP, Deep Trench, High Linearity MiM, Schottky Barrier Diode, ULL N/PMOS.

UMC MPW
Jan
Feb
Mar
Apr
May
Jun
Jul
Aug
Sep
Oct
Nov
Dec
UMC 28N Logic/Mixed-Mode – HPC
6
15
10
16
UMC 40N Logic/Mixed-Mode – LP
30
6
29
28
30
UMC 65N Logic/Mixed-Mode/RF – LL
16
13
12
4
6
UMC 55N Logic/Mixed-Mode/RF – SP
16
13
1
12
4
6
UMC L110AE Logic/Mixed-Mode/RF
23
3
22
31
2
27
UMC L180 Logic GII
27
7
13
UMC L180 Mixed-Mode/RF
27
7
13

Important notes: Dates are GDS submission deadlines. Design registration must be done at least 3 weeks in advance.

 

Additional technology options are available:

X-FAB MPW
Jan
Feb
Mar
Apr
May
Jun
Jul
Aug
Sep
Oct
Nov
Dec
XH018 0.18µ HV NVM CMOS E-FLASH
27
10
23
XT018 0.18µ HV SOI CMOS
13
12
14
6
XS018 0.18µ OPTO *
20
31
XP018 0.18µ NVM CMOS *
6
29
2
XH035 0.35µ HV CMOS
9
28
4
3
XR013 0.13µ RF SOI CMOS *
13
5
21
6
XMB10 MEMS
15

Important notes: Dates are GDS submission deadlines. Registration should be done at least 2 weeks in advance.

* In case of cancellation, there is a possibility to order these technologies by MLM.

 

Please take a look at additional technology options:

imec MPW
Jan
Feb
Mar
Apr
May
Jun
Jul
Aug
Sep
Oct
Nov
Dec
imec Si-Photonics Passives+
17
imec Si-Photonics iSiPP50G
8
20
imec GaN-IC on SOI 200V
19
GaN-IC on SOI 650V
20

Important notes: Dates indicate deadlines for submission of the first version of the GDS file.
Design registration should be done at least 4 weeks in advance.

Admin. procedure should be finished at least 1 week before the dates indicated in the table.

MEMSCAP MPW
Jan
Feb
Mar
Apr
May
Jun
Jul
Aug
Sep
Oct
Nov
Dec
PolyMUMPs
21
SOIMUMPS
28
4
31
PiezoMUMPS
3
9
5

Important notes: Dates indicate deadlines for both Registration and submission of the first version of the GDS file.