13 Jun TSMC28 and Si-Photonics – University of Southampton, UK
Co-design of electronics and photonics components for Silicon Photonics transmitters
University of Southampton, UK
TSMC 28nm HPL + Silicon Photonics
1570μm × 1570µm
We present an approach (DOI: 10.1109/ECOC.2018.8535212) where photonic and electronic devices are co-designed synergistically in terms of power efficiency, operation speed, footprint and signal integrity. To justify the advantages of this concept, we have demonstrated a silicon photonics transmitter, which incorporates a co-designed depletion-type silicon Mach-Zehnder modulator (Si MZM) and a 28nm Complementary Metal–Oxide–Semiconductor (CMOS) driver.
Thanks to the technique support from EUROPRACTICE, we got tremendous success with our first time TSMC 28nm HKMG-CMOS tape-out via the mini@sic programme. These 28nm CMOS driver chips are then integrated (both wire-bonding and flip-chip bonding) with silicon photonics modulator at nanofabrication center, Optoelectronics Research Centre (ORC), University of Southampton.
Simply based on the wire-bonding approach, the proposed transmitter can operate up to 22Gb/s with the CMOS driver power efficiency at 1.5pJ/bit, with a 3.0dB extinction ratio maintained. Further measurement results based on the flip-chip bonding approach have demonstrated operation speed up to 40Gb/s with the CMOS driver power efficiency at 2.46pJ/bit, with a clear eye-open and 2.9dB extinction ratio.
The financial support of the EPSRC, UK under the grants EP/L00044X/1 (Silicon Photonics for Future Systems) and EP/L021129/1(CORNERSTONE: Capability for OptoelectRoNics, mEtamateRialS, nanoTechnOlogy aNd sEnsing) is gratefully acknowledged. Dr. David Thomson gratefully acknowledges funding from the Royal Society for his University Research Fellowship
The University of Southampton has worked with EUROPRACTICE on TSMC fabrication for many years. We have benefitted from EUROPRACTICE’S excellent technical support for CMOS chip submission. EUROPRACTICE has given us affordable access to frequent multi-project wafer fabrication runs.