GF SiGe 8XP | |||
|---|---|---|---|
Technology characteristics | Core voltage: 1.2V / 2.5V I/O voltage: 1.5 / 1.8V / 2.5V / 3.3V TSV Metal layers: 5 – 7 of Cu and AI Thick Al and Cu “MA” add-on module for high Q inductors Forward Bias, PIN and Schottky Barrier Diodes High performance SiGe NPN transistors (fT/fmax 250/340GHz) High breakdown fT= 78GHz, 3.2V BVceo Temperature Range: -55°C to 125°C Device offerings: SchottkyDiode, P+ poly resistors, Thin oxide NMOS varactor/ decoupling capacitor, Spiral inductors, Transmission lines, mmWave passive elements, eFuse, Triple-well NFETs, PIN Diode, Hyper abrupt (HA) varactor, MIM capacitor, Dual MIM (3 fF/μm2), High-RsRR poly resistor, TaNmetal KQ resistor, True triple well (T3) FET | ||
Wafer size | 12inch | ||
Manufacturing location | Fab9 – Burlington, Vermont, USA
| ||
Deliverables
| 50 bare dies
| ||
Signoff tools
| Cadence, Siemens EDA
| ||
Foundational IPs
| Standard cell libraries: GLOBALFOUNDRIES GPIO : GLOBALFOUNDRIES SRAM : ARM / GLOBALFOUNDRIES The ARM IPs have to be requested directly at ARM via DesignStart portal For GLOBALFOUNDRIES IPs contact Fraunhofer IIS | ||
Dummy filling
| To be done by the customer
| ||
MPW block size
| 9mm² with a min. edge length of 1mm, flexible aspect ratio
| ||
Turnaround time
| ca. 6 months
| ||
mini@sic characteristics
| Not supported
| ||
Bumping
| Cu Pillar and SnAg
| ||
GF SiGe 8XP | |||
|---|---|---|---|
Technology characteristics | Core voltage: 1.2V / 2.5V I/O voltage: 1.5 / 1.8V / 2.5V / 3.3V TSV Metal layers: 5 – 7 of Cu and AI Thick Al and Cu “MA” add-on module for high Q inductors Forward Bias, PIN and Schottky Barrier Diodes High performance SiGe NPN transistors (fT/fmax 250/340GHz) High breakdown fT= 78GHz, 3.2V BVceo Temperature Range: -55°C to 125°C Device offerings: SchottkyDiode, P+ poly resistors, Thin oxide NMOS varactor/ decoupling capacitor, Spiral inductors, Transmission lines, mmWave passive elements, eFuse, Triple-well NFETs, PIN Diode, Hyper abrupt (HA) varactor, MIM capacitor, Dual MIM (3 fF/μm2), High-RsRR poly resistor, TaNmetal KQ resistor, True triple well (T3) FET | ||
Wafer size | 12inch | ||
Manufacturing location | Fab9 – Burlington, Vermont, USA
| ||
Deliverables
| 50 bare dies
| ||
Signoff tools
| Cadence, Siemens EDA
| ||
Foundational IPs
| Standard cell libraries: GLOBALFOUNDRIES GPIO : GLOBALFOUNDRIES SRAM : ARM / GLOBALFOUNDRIES The ARM IPs have to be requested directly at ARM via DesignStart portal For GLOBALFOUNDRIES IPs contact Fraunhofer IIS | ||
Dummy filling
| To be done by the customer
| ||
MPW block size
| 9mm² with a min. edge length of 1mm, flexible aspect ratio
| ||
Turnaround time
| ca. 6 months
| ||
mini@sic characteristics
| Not supported
| ||
Bumping
| Cu Pillar and SnAg
| ||
45RFSOI takes advantage of a 45nm partially-depleted SOI server-class technology base that has been extensively evaluated for use in mmWave applications and in high volume production at multiple GF fabs since 2008. Today, this baseline process has RFcentric enablement, topped with device and technology additions, including thick copper and dielectric back-end-of-line (BEOL) features which enable 45RFSOI to handle the demanding performance requirements of 5G solutions.
GF 45RFSOI | |
|---|---|
Technology characteristics | High-resistivity substrate ≥7500 Ω-cm Three BEOL STACK options: 7 or 8 Levels of Cu Wiring and Thick Al LD or LB Operating junction temperature: -40°C to 125°C VDD of 0.9 V or 1.0 V (thin oxide) Two gate oxide thicknesses High density / High Q MIMcap, High-value resistor RF and mmWave offering: Inductors, Microstrip, Coplanar Waveguides, Passives Fuse: eFuse |
Wafer size | 12inch |
Manufacturing location | FAB8 – USA |
Deliverables
| 45-50 Dies (depends on 3rd party packaging services)
|
Signoff tools
| Cadence, Siemens EDA
|
Foundational IPs
| Standard cell libraries: ARM GPIO : ARM SRAM : N/A The foundational IPs have to be requested directly at ARM via DesignStart portal |
Dummy filling
| To be done by the customer
|
MPW block size
| 12mm² |
Turnaround time
| ca. 5.5 months
|
mini@sic characteristics
| Supported for universities and research institutes Block size: min. 1mm2 |
Bumping
| Available only for general MPW (Cu Pillar and SnAg)
|
GF SiGe 8XP | |||
|---|---|---|---|
Technology characteristics | Core voltage: 1.2V / 2.5V I/O voltage: 1.5 / 1.8V / 2.5V / 3.3V TSV Metal layers: 5 – 7 of Cu and AI Thick Al and Cu “MA” add-on module for high Q inductors Forward Bias, PIN and Schottky Barrier Diodes High performance SiGe NPN transistors (fT/fmax 250/340GHz) High breakdown fT= 78GHz, 3.2V BVceo Temperature Range: -55°C to 125°C Device offerings: SchottkyDiode, P+ poly resistors, Thin oxide NMOS varactor/ decoupling capacitor, Spiral inductors, Transmission lines, mmWave passive elements, eFuse, Triple-well NFETs, PIN Diode, Hyper abrupt (HA) varactor, MIM capacitor, Dual MIM (3 fF/μm2), High-RsRR poly resistor, TaNmetal KQ resistor, True triple well (T3) FET | ||
Wafer size | 12inch | ||
Manufacturing location | Fab9 – Burlington, Vermont, USA
| ||
Deliverables
| 50 bare dies
| ||
Signoff tools
| Cadence, Siemens EDA
| ||
Foundational IPs
| Standard cell libraries: GLOBALFOUNDRIES GPIO : GLOBALFOUNDRIES SRAM : ARM / GLOBALFOUNDRIES The ARM IPs have to be requested directly at ARM via DesignStart portal For GLOBALFOUNDRIES IPs contact Fraunhofer IIS | ||
Dummy filling
| To be done by the customer
| ||
MPW block size
| 9mm² with a min. edge length of 1mm, flexible aspect ratio
| ||
Turnaround time
| ca. 6 months
| ||
mini@sic characteristics
| Not supported
| ||
Bumping
| Cu Pillar and SnAg
| ||
GF SiGe 8XP | |||
|---|---|---|---|
Technology characteristics | Core voltage: 1.2V / 2.5V I/O voltage: 1.5 / 1.8V / 2.5V / 3.3V TSV Metal layers: 5 – 7 of Cu and AI Thick Al and Cu “MA” add-on module for high Q inductors Forward Bias, PIN and Schottky Barrier Diodes High performance SiGe NPN transistors (fT/fmax 250/340GHz) High breakdown fT= 78GHz, 3.2V BVceo Temperature Range: -55°C to 125°C Device offerings: SchottkyDiode, P+ poly resistors, Thin oxide NMOS varactor/ decoupling capacitor, Spiral inductors, Transmission lines, mmWave passive elements, eFuse, Triple-well NFETs, PIN Diode, Hyper abrupt (HA) varactor, MIM capacitor, Dual MIM (3 fF/μm2), High-RsRR poly resistor, TaNmetal KQ resistor, True triple well (T3) FET | ||
Wafer size | 12inch | ||
Manufacturing location | Fab9 – Burlington, Vermont, USA
| ||
Deliverables
| 50 bare dies
| ||
Signoff tools
| Cadence, Siemens EDA
| ||
Foundational IPs
| Standard cell libraries: GLOBALFOUNDRIES GPIO : GLOBALFOUNDRIES SRAM : ARM / GLOBALFOUNDRIES The ARM IPs have to be requested directly at ARM via DesignStart portal For GLOBALFOUNDRIES IPs contact Fraunhofer IIS | ||
Dummy filling
| To be done by the customer
| ||
MPW block size
| 9mm² with a min. edge length of 1mm, flexible aspect ratio
| ||
Turnaround time
| ca. 6 months
| ||
mini@sic characteristics
| Not supported
| ||
Bumping
| Cu Pillar and SnAg
| ||
GF SiGe 8XP | |||
|---|---|---|---|
Technology characteristics | Core voltage: 1.2V / 2.5V I/O voltage: 1.5 / 1.8V / 2.5V / 3.3V TSV Metal layers: 5 – 7 of Cu and AI Thick Al and Cu “MA” add-on module for high Q inductors Forward Bias, PIN and Schottky Barrier Diodes High performance SiGe NPN transistors (fT/fmax 250/340GHz) High breakdown fT= 78GHz, 3.2V BVceo Temperature Range: -55°C to 125°C Device offerings: SchottkyDiode, P+ poly resistors, Thin oxide NMOS varactor/ decoupling capacitor, Spiral inductors, Transmission lines, mmWave passive elements, eFuse, Triple-well NFETs, PIN Diode, Hyper abrupt (HA) varactor, MIM capacitor, Dual MIM (3 fF/μm2), High-RsRR poly resistor, TaNmetal KQ resistor, True triple well (T3) FET | Core voltage: 1.2V / 2.5V I/O voltage: 1.5 / 1.8V / 2.5V / 3.3V TSV Metal layers: 5 – 7 of Cu and AI Thick Al and Cu “MA” add-on module for high Q inductors Forward Bias, PIN and Schottky Barrier Diodes High performance SiGe NPN transistors (fT/fmax 250/340GHz) High breakdown fT= 78GHz, 3.2V BVceo Temperature Range: -55°C to 125°C Device offerings: SchottkyDiode, P+ poly resistors, Thin oxide NMOS varactor/ decoupling capacitor, Spiral inductors, Transmission lines, mmWave passive elements, eFuse, Triple-well NFETs, PIN Diode, Hyper abrupt (HA) varactor, MIM capacitor, Dual MIM (3 fF/μm2), High-RsRR poly resistor, TaNmetal KQ resistor, True triple well (T3) FET | Core voltage: 1.2V / 2.5V I/O voltage: 1.5 / 1.8V / 2.5V / 3.3V TSV Metal layers: 5 – 7 of Cu and AI Thick Al and Cu “MA” add-on module for high Q inductors Forward Bias, PIN and Schottky Barrier Diodes High performance SiGe NPN transistors (fT/fmax 250/340GHz) High breakdown fT= 78GHz, 3.2V BVceo Temperature Range: -55°C to 125°C Device offerings: SchottkyDiode, P+ poly resistors, Thin oxide NMOS varactor/ decoupling capacitor, Spiral inductors, Transmission lines, mmWave passive elements, eFuse, Triple-well NFETs, PIN Diode, Hyper abrupt (HA) varactor, MIM capacitor, Dual MIM (3 fF/μm2), High-RsRR poly resistor, TaNmetal KQ resistor, True triple well (T3) FET |
Wafer size | 12inch | ||
Manufacturing location | Fab9 – Burlington, Vermont, USA
| ||
Deliverables
| 50 bare dies
| ||
Signoff tools
| Cadence, Siemens EDA
| ||
Foundational IPs
| Standard cell libraries: GLOBALFOUNDRIES GPIO : GLOBALFOUNDRIES SRAM : ARM / GLOBALFOUNDRIES The ARM IPs have to be requested directly at ARM via DesignStart portal For GLOBALFOUNDRIES IPs contact Fraunhofer IIS | ||
Dummy filling
| To be done by the customer
| ||
MPW block size
| 9mm² with a min. edge length of 1mm, flexible aspect ratio
| ||
Turnaround time
| ca. 6 months
| ||
mini@sic characteristics
| Not supported
| ||
Bumping
| Cu Pillar and SnAg
| ||
