EUROPRACTICE | Wafer-level services

Multi-Project Fan-Out Wafer Level Packaging

OPEN 3D post-process for 3D integration

CMP, in partnership with CEA-LETI, offers a set of post-processes allowing various types of 3D assemblies.

These wafer-level services are available only for the customers of the EUROPRACTICE partner CMP.

Those post-processes are operated at wafer-level and are carried out after standard MPW runs on a selected subset of technologies. The goal is to integrate 3D interconnections to chips processed through CMP, in order to enable flip-chip on organic or ceramic substrates as well as Die-to-Die or Die-to-Interposer assemblies.

Two types of post-processes are available, including different options:

Front-side: 3D interconnections (µ-Bumps or UBM).
Back-side: Wafer thinning, TSV (via-last) and RDL, 3D interconnections (Bumps).

Technology characteristics:

µBumps (Cu-pillar)	Cu/SnAg ; ø25 µm ; 50 µm min pitch ; ~20 µm thickness
UBM	TiNiAu ; 25 µm min width; 50 µm min pitch ; 1 µm thickness
TSV-LAST	Ø60 µm x 120 µm depth ; 120 µm min pitch
Backside RDL	Cu ; 20 µm min width ; 40 µm min pitch ; 4-8 µm Thickness

Accessibility conditions:

As a MPW OPEN3D Front‐side post process (μ‐Bumps or UBM)
As a MPW OPEN3D Back‐side post process (TSV, RDL and Bumps)
As a MPW OPEN3D Back‐side + Front‐side post process (μ‐Bumps or UBM + TSV, RDL and Bumps)

MPW OPEN 3D post processes are available for projects and wafers processed through CMP on the last CMP MPW run of the year for the following technologies:

ams	C35B4M3
CEA-LETI	Silicon Photonics
STMicroelectronics	CMOS28FDSOI (frontside only), BiCMOS055, CMOS065, BiCMOS9MW

Those runs are subject to a certain minimum number of participants sharing the MPW.

MPW OPEN 3D post‐processes must be anticipated at an early stage as they require an additional NDA, the distribution of a specific DRM and an add‐on to the Design‐Kit. Additionaly, this must be indicated it in the reservation form.

As a dedicated OPEN3D post‐process

Dedicated OPEN3D post processes can be made available on any CMP MPW Run at any time of the year after a feasibility study. In this case, restrictions to specific geometrical parameters of the design structure are not imposed and can be chosen within a process window. Please contact CMP for more information/quotation.

Application area:
3D/2.5D integration

Design kit version:

CMP/LETI 3D add-on is required to design post-processed modules

Verification tools:

DRC calibre die-level; DRC calibre 3Dstack for assembly-level checks (at CMP only)

Libraries:
3D modules Library

Packaging:
OPEN 3D post processing is available upon request, please contact ajith-sivadasan.moreau@mycmp.fr for more information on packaging solutions.

Technology characteristics	Solder bumping consists in manufacturing metal spheres acting as interconnections for flip-chip. Those spheres are composed of a Sn/Ag/Cu alloy (SAC). Before the sphere can be deposited, the deposition of an Under Bump Metalization (UBM) layer is required. This option, available on ams 0.35 & 0.18 runs only, is operated at wafer-level within ams cleanroom after CMOS process. It allows the deposition of an array of solder balls at wafer-level, with an I/O pitch compatible with traditional printed circuit board (PCB) assembly processes. For mechanical reasons solder balls are usually evenly distributed over the whole chip surface and electrically connected to the IC‘s CMOS pads by means of a redistribution layer (RDL) included in the option.
Application area	Single die flip-chip packaging
Design Kit version	Option supported by ams hitkit 4.10 ISR15, through an add-on

News & Events

Schedules and Prices

Wafer-level services

Multi-Project Fan-Out Wafer Level Packaging

OPEN 3D post-process for 3D integration

ams 0.35µm Wafer-level bumping

STMicroelectronics Wafer-level bumping