SCHEDULES & PRICES

2024

Schedules 2024

GENERAL MPW & MINI@SIC SCHEDULES - 2024

Here you can find General MPW and mini@sic run schedules and pricelists for 2024.

To reserve your seat on a run, please register your design in the Registration Form or contact the Europractice partner responsible for the technology.

PRICELISTS - 2024

There are two prices in the Europractice lists: Discounted and Standard.

DISCOUNTED PRICE

Three conditions should be met for Discounted prices:

Customer is an academic institution or a research facility from one of the 27 EU countries together with Albania, Armenia, Azerbaijan, Bosnia-Herzegovina, Georgia, Iceland, Israel, Liechtenstein, North Macedonia, Moldova, Montenegro, Norway, Switzerland, Turkey, Serbia, the UK and Ukraine.
Customer is a registered Europractice member who has paid the Full-IC annual membership fee.
The intended design will be done for educational purposes or for publicly funded research.

STANDARD PRICE

Standard prices apply to all other customers.

ams OSRAM MPW	Feb	Apr	May	Jul	Oct	Nov
ams OSRAM 0.35µ CMOS C35B4C3 4M/2P/HR/5V IO	26			15		4
ams OSRAM 0.35µ CMOS C35OPTO 4M/2P/5V	26			15		4
ams OSRAM 0.35µ HV CMOS H35B4D3 120V 4M			13*			25*
ams OSRAM 0.35µ SiGe-BiCMOS S35D4M5 / CMOS-RF C35B4M3 4M/4P Thick MET4 – MIM					7**
ams OSRAM 0.18µ CMOS atC18C6SH 6M/1P/HR/MIM/TW (Triple-well), 1.8V/3.3V		29			21

Important notes: Dates are GDS submission deadlines. Design registration must be done at least 2 weeks in advance.

* MPW run on request

** Last offered MPW run

ams OSRAM MPW Pricelist	Standard EUR / mm²	Discounted EUR / mm²
ams OSRAM 0.35µ CMOS C35B4C3 4M/2P/HR/5V IO	640¹	580¹
ams OSRAM 0.35µ CMOS C35OPTO 4M/2P/5V	800²	700²
ams OSRAM 0.35µ HV CMOS H35B4D3 120V 4M	880¹	800¹
ams OSRAM 0.35µ SiGe-BiCMOS S35D4M5 /CMOS-RF C35B4M3 4M/4P Thick MET4 – MIM	880¹	800¹
ams OSRAM 0.18µ CMOS atC18C6SH 6M/1P/HRP/TW (Triple-well), 1.8V/3.3V	1,650³	1,500³

Important notes:

¹ Price = area (mm²) * price/mm² with min. fabrication cost equivalent to 10mm²

²Price = area (mm²) * price/mm²with min. fabrication cost equivalent to 20mm²

³Price = area (mm²) * price/mm²with min. fabrication cost equivalent to 5.5mm²

Fraunhofer IISB		Jan	Feb	Mar	Apr	May	Jun	Jul	Aug	Sep	Oct	Nov	Dec
4H-SiC CMOS HIGH TEMPERATURE			9

Important notes: Dates are GDS submission deadlines. Design registration must be done at least 4 weeks in advance.

The first design submission (for our review and feedback) must be done on 12 January 2024.

Fraunhofer IISB Pricelist		Standard EUR / block	Discount EUR / block
4H-SiC CMOS HIGH TEMPERATURE (2.5mm x 5mm)¹		10,500	9,500
4H-SiC CMOS HIGH TEMPERATURE (5mm x 5mm)²		20,500	18,500

Important notes:
¹Max. design surface: 2.35mm x 4.85mm

²Max. design surface: 4.85mm x 4.85mm

Larger chip sizes and pricing are available on request.

GLOBALFOUNDRIES MPW	Jan	Feb	Mar	Apr	Jun	Jul	Aug	Sep	Oct	Nov	Dec
GLOBALFOUNDRIES SiGe 8XP			19		18			10			8
GLOBALFOUNDRIES 130nm BCDlite – Gen2			11					9
GLOBALFOUNDRIES 55 nm BCDlite			25		25			17
GLOBALFOUNDRIES 45RFE		13					13
GLOBALFOUNDRIES 45nm RFSOI									1
GLOBALFOUNDRIES 45nm SPCLO – Silicon Photonics		14						3
GLOBALFOUNDRIES 28 nm SLPe			25						7
GLOBALFOUNDRIES 22 nm FDSOI	8	26		15	10	29		23		15
GLOBALFOUNDRIES 12 nm LP+	10						14

Important notes: Dates are Registration deadlines after which designs cannot be accepted.

Final GDSII file must be submitted within 6 weeks after this date.

Dates in red are preliminary.

A cancellation fee is applicable if the registration is cancelled later than 2 weeks after the Registration deadline or if the customer is unable to provide a DRC-clean GDS before the Tapeout deadline.

GLOBALFOUNDRIES MPW Pricelist	Standard EUR / mm²	Discounted EUR / mm²
GLOBALFOUNDRIES SiGe 8XP	4,230 ¹	4,050 ¹
GLOBALFOUNDRIES 130 nm BCDlite	1,710 ²	1,620 ²
GLOBALFOUNDRIES 55 nm BCDlite	4,950 ¹	4,680 ¹
GLOBALFOUNDRIES 45RFE	9,180 ¹	8,820¹
GLOBALFOUNDRIES 45RFSOI	9,180 ¹	8,820¹
GLOBALFOUNDRIES 45nm SPCLO -Silicon Photonics (price per fixed block 5mm x 5mm)	231,000	220,000
GLOBALFOUNDRIES 28 nm SLPe	10,890 ³	10,350 ³
GLOBALFOUNDRIES 22 nm FDSOI	16,110 ³	15,300 ³
GLOBALFOUNDRIES 12 nm LP+	26,460 ³	25,200 ³

Important notes:

¹ Price = area (mm²) * price/mm² with min. fabrication cost equivalent to 12 mm². Any edge length between 1.0 mm to 11 mm is possible.

The mentioned die size is referred to the Pre-Shrink die size.

² Price = area (mm²) * price/mm² with min. fabrication cost equivalent to 25 mm². Any edge length between 1.0 mm to 11 mm is possible.

The mentioned die size is referred to the Pre-Shrink die size.

³ Price = area (mm²) * price/mm² with min. fabrication cost equivalent to 9 mm². Any edge length between 1.0 mm to 11 mm is possible.

The mentioned die size is referred to the Pre-Shrink die size.

GLOBALFOUNDRIES mini@sic	Jan	Feb	Mar	Apr	Jun	Jul	Aug	Sep	Oct	Nov	Dec
GLOBALFOUNDRIES SiGe 8XP			19		18			10			8
GLOBALFOUNDRIES 130nm BCDlite – Gen2			11					9
GLOBALFOUNDRIES 55 nm BCDlite			25		25			17
GLOBALFOUNDRIES 45RFE		13					13
GLOBALFOUNDRIES 45nm RFSOI									1
GLOBALFOUNDRIES 45nm SPCLO – Silicon Photonics		14						3
GLOBALFOUNDRIES 28 nm SLPe			25						8
GLOBALFOUNDRIES 22 nm FDSOI	8	26		15	10	29		23		15
GLOBALFOUNDRIES 12 nm LP+	10						14

Important notes: The mini@sic model of GlobalFoundries is available only for universities and research institutes.

Dates are Registration deadlines after which designs cannot be accepted.

Final GDSII file must be submitted within 6 weeks after this date.

Dates in red are preliminary.

GLOBALFOUNDRIES mini@sic Pricelist	Standard EUR / mm²	Discounted EUR / mm²
GLOBALFOUNDRIES SiGe 8XP	7,260 ¹	6,600 ¹
GLOBALFOUNDRIES 130nm BCDlite – Gen2	3,080 ²	2,800 ²
GLOBALFOUNDRIES 55 nm BCDlite	8,250 ¹	7,500 ¹
GLOBALFOUNDRIES 45RFE	13,200 ¹	12,000 ¹
GLOBALFOUNDRIES 45RFSOI	13,200 ¹	12,000 ¹
GLOBALFOUNDRIES 45nm SPCLO -Silicon Photonics	154,000 ⁴	140,000 ⁴
GLOBALFOUNDRIES 28 nm SLPe	18,370 ³	16,700 ³
GLOBALFOUNDRIES 22 nm FDSOI	25,080 ³	22,800 ³
GLOBALFOUNDRIES 12 nm LP+	38,500 ³	35,000 ³

Important notes:

¹ Price = area (mm²) * price/mm² with min. fabrication cost equivalent to 2.5 mm². The mentioned die size is referred to the Pre-Shrink die size.

² Price = area (mm²) * price/mm² with min. fabrication cost equivalent to 5 mm². The mentioned die size is referred to the Pre-Shrink die size.

³ Price = area (mm²) * price/mm² with min. fabrication cost equivalent to 1 mm².The mentioned die size is referred to the Pre-Shrink die size.

⁴ Price = fixed block size of 5mm x 2.455mm or 2.455mm x 5mm.

IHP MPW	Feb	Mar	May	Jul	Oct	Nov
IHP SG13C SiGe:C RF CMOS			10	19		22
IHP SG13G2 SiGe:C Bipolar/Analog			10	19		22
IHP SG13G2Cu (FEOL process SG13G2 + Cu BEOL option from X-FAB)		1		19		22
IHP SG13G3Cu (FEOL process + Cu BEOL option from X-FAB)				19		22
IHP SG13G3 (FEOL process SG13G3Cu + Al-BEOL option)*				19		22
IHP SG13S SiGe:C Bipolar/Analog			10	19		22
IHP SG13SCu (FEOL process SG13S + Cu BEOL option from X-FAB)		1		19		22
IHP MEMRES for SG13S			10			22
IHP SG25 PIC (Photonics, Ge Photo-diode, BEOL)				26
IHP SG25H5_EPIC high performance BiCMOS + Photonic					18
IHP BEOL SG13 (M1 and Metal Layers Above) + optional LBE or TSV or RDL	9

Important notes: Dates are Registration deadlines. Final GDSII file must be submitted within 10 calendar days after this date.

The final chip area may not deviate by more than 5% from the registered area including the sealring.

* For research and prototyping purposes only.

MEMRES is available for IHP SG13S technology with extra charge.

TSV and RDL are available for IHP SG13S and SG13G2 technologies with extra charge.

Cu Pillar and Bumping are available for all IHP technologies with extra charge; SG13C on request.

Local Backside Etching (LBE) is not offered for EPIC runs and runs with Cu-BEOL.

IHP MPW Pricelist	Standard EUR / mm²	Discounted EUR / mm²
IHP SG13C SiGe:C RF CMOS	4,500 ¹	3,825 ¹
IHP SG13G2 SiGe:C Bipolar/Analog	7,300 ¹	6,205 ¹
IHP SG13G2Cu (FEOL process SG13G2 + Cu BEOL option from X-FAB)	7,300 ^1,	6,205 ¹
IHP SG13G3Cu (FEOL process + Cu BEOL option from X-FAB)	9000 ¹	7,650 ¹
IHP SG13G3 (FEOL process SG13G3Cu + Al-BEOL option)*	9,000 ¹	7,650 ¹
IHP SG13S SiGe:C Bipolar/Analog	6,300 ¹	5,355 ¹
IHP SG13SCu (FEOL process SG13S + Cu BEOL option from X-FAB)	6,300 ¹	5,355 ¹
IHP SG25 PIC (Photonics, Ge Photo-diode, BEOL)	3,800 ^1,3	3,230 ^1,3
IHP SG25H5_EPIC high performance BiCMOS + Photonic	8,000 ^1,3	6,800 ^1,3
IHP BEOL SG13 (M1 and Metal Layers Above) + optional LBE or TSV or RDL	1,000 ¹	850 ¹
IHP Special Services
Bumping (available for all IHP technologies), SG13C on request	6,500²	6,500 ²
Localized Back side Etching (available for IHP technologies with AL BEOL only), not offered for EPIC/PIC runs	5,000²	4,250 ²
TSV to ground (SG13S / G2)	12,500 ²	10,625 ²
Cu Pillar	18,500²	on request
MEMRES Module one time fee for SG13S only	2,500²	2,000²
MEMRES Module additional fee per mm² for SG13S only	600¹	510¹
TSV_RDL Module one time fee for SG13S and SG13G2	27,000²

Important notes:

¹ Price = area (mm²) * price/mm² with min. fabrication cost equivalent to 0.8mm².
The chip area is inclusive of the filler cells outside the seal ring.
² One-off fee
³ Delivery quantity: 25 dies.

Fabrication of a chip area less than 0.8mm² and X & Y ratio larger than 1:3 is on request.

* For research and prototyping purposes only.

Standard MPW price is meant for designs of industrial customers.

Discounted MPW price is meant for designs created for educational purposes or publicly funded research for non-EU countries.

IHP mini@sic	Feb	Mar	May	Jul	Oct	Nov
IHP SG13C SiGe:C RF CMOS			10	19		22
IHP SG13G2 SiGe:C Bipolar/Analog			10	19		22
IHP SG13G2Cu (FEOL process SG13G2 + Cu BEOL option from X-FAB)		1		19		22
IHP SG13G3Cu (FEOL process + Cu BEOL option from X-FAB)				19		22
IHP SG13G3 (FEOL process SG13G3Cu + Al-BEOL option)*				19		22
IHP SG13S SiGe:C Bipolar/Analog			10	19		22
IHP SG13SCu (FEOL process SG13S + Cu BEOL option from X-FAB)		1		19		22
IHP MEMRES for SG13S			10			22
IHP SG25 PIC (Photonics, Ge Photo-diode, BEOL)				26
IHP SG25H5_EPIC high performance BiCMOS + Photonic					18
IHP BEOL SG13 (M1 and Metal Layers Above) + optional LBE or TSV or RDL	9

Important notes: Dates are Registration deadlines. Final GDSII file must be submitted within 10 calendar days after this date.

The final chip area may not deviate by more than 5% from the registered area including the sealring.

* For research and prototyping purposes only.

MEMRES is available for IHP SG13S technology with extra charge.

TSV and RDL are available for IHP SG13S and SG13G2 technologies with extra charge.

Cu Pillar and Bumping are available for all IHP technologies with extra charge; SG13C on request.

Local Backside Etching (LBE) is not offered for EPIC runs and runs with Cu-BEOL.

IHP mini@sic Pricelist	Standard EUR / mm²	Discounted EUR / mm²
IHP SG13S SiGe:C Bipolar/Analog, Ft/Fmax= 250/340GHz, 7M/MIM	5,355 ¹	4,410 ¹
IHP SG13SCu FEOL process SG13S together with 8 layer Cu BEOL from X-FAB containing 4 thin & 2 thick Cu layers, a thin Al layer and Al top layer.	5,355 ¹	4,110 ¹
IHP SG13CMOS SiGe:C includes all features of SG13G2 but not HBT, CMOS 7M/MIM, PDK von SG13G2	3,825 ^1,	3,600 ¹
IHP SG13CMOS5L SiGe:C A CMOS technology offered for open-source education designs, includes FEOL SG13CMOS, but noisolated NMOS, 4 thin metal layer and one 2μm thick TopMetal and no MIM capacitor
IHP SG13G2 SiGe:C Bipolar/Analog, Ft/Fmax= 350/450GHz, 7M/MIM	6,205 ¹	5,110¹
IHP SG13G2Cu FEOL process SG13G2 together with 8 layer Cu BEOL from X-FAB containing 4 thin & 2 thick Cu layers, a thin Al layer and Al top layer.	6,205 ¹	5,110 ¹
IHP SG13G3 FEOL, the same FEOL process SG13G3Cu, with Al-BEOL option for research and prototyping purpose only	7,650 ¹	6,300¹
IHP SG13G3Cu SiGe:C Bipolar/Analog, Ft/Fmax= 470/650GHz FEOL process with 8 layer Cu BEOL from X-FAB containing 4 thin & 2 thick Cu layers, a thin Al layer and Al top layer	7,650 ¹	6,300 ¹
IHP BEOL SG13 (M1 and Metal Layers Above)	1170 ¹	1170 ¹
SG25H7_EPIC A monolithic photonic BiCMOS technology combining CMOS, high-performance npn HBTs (fT / fmax = >350/>500 GHz), and full photonic device set for C/O-band., 7M/MIM,Ge Photo-diode	7,650 ^1,3	6,750 ^1,3
IHP SG25H7_PIC Incl. additional photonic design layers along with BiCMOS BEOL layers on SOI wafers.	3,825 ^1,3	3,600 ^1,3
IHP INTM4TM2 Interposer technology, 2 thin and 2 thick Al-BEOL layer on a HRes substrate, MIM capacitor, Thin film Res.	765	720
IHP Special Services
Bumping (available for all IHP technologies), SG13C on request	on request²	on request²
Localized Back side Etching (available for IHP technologies with AL BEOL only), not offered for EPIC/PIC runs	4,250²	2,500 ²
TSV to ground (SG13S / G2)	10,625 ²	7,500 ²
Cu Pillar	on request²	on request²
MEMRES Module, CMOS integrated memristive module based on resistive TiN / HfO2-x / TiN switching devices, on time fee offered for SG13G2	2,000²	2,000²
MEMRES Module additional fee per mm²	510¹	450¹

Important notes:

Fabrication of a chip area less than 0.8mm² and X & Y ratio larger than 1:3 is on request.

* For research and prototyping purposes only.

Standard mini@sic price is meant for designs created for educational purposes or publicly funded research for non-EU countries.

Discounted mini@sic price is meant for designs created for educational purposes or publicly funded research for the EU countries.

STMicroelectronics MPW	May	Jul	Sep	Oct	Nov
ST 28nm CMOS28FDSOI				1
ST 28nm CMOSP28FDSOI	24
ST 55nm BiCMOS055X		5			4
ST 65nm CMOS065				1*
ST 130nm BiCMOS9MW			2
ST 130nm HCMOS9A			2		4
ST 130nm SOI H9SOI-FEM			2*
ST 0.16µm BCD8sP	20		2
ST 0.16µm BCD8s-SOI		1*

Important notes: Dates are GDS submission deadlines. Design registration has to be done at least 4 weeks in advance.

* MPW run on request. Please contact cime-prototypage@grenoble-inp.fr

Dates in red are preliminary.

TSMC MPW	Jan	Feb	Mar	Apr	May	Jun	Jul	Aug	Sep	Oct	Nov	Dec
TSMC 0.13µm CMOS BCD plus (12-inch)	17				8		24				6
TSMC 0.13µm CMOS Logic or MS/RF, GP or LP (12-inch)	17				8		24				6
TSMC 90nm CMOS Logic or MS/RF, GP or LP			6			12		7				4
TSMC 65nm CMOS Logic or MS/RF, GP or LP		7	27		22	26			18		20
TSMC 40nm CMOS Logic or MS/RF, LP (no triple gate oxide)		7 21	27	24	29		24	28	25	23	20
TSMC 40nm CMOS Logic or MS/RF, GP (no triple gate oxide)		21		24				28		23
TSMC 28nm CMOS Logic or RF HPC/HPC+	3	7 28			1 29		31		4	30	27	18
TSMC 22nm CMOS Logic or RF ULL		21	27	24		26		21		2 23		18
TSMC 16nm CMOS Logic or RF FinFET Compact		7		3	22		24		18		27
TSMC 7nm CMOS Logic or RF FinFET	3			3						2		18

Important notes:

Dates are GDS submission deadlines.

Several TSMC shuttles are extremely loaded. For any technology, please make your design registration as early as possible. We will work with you and do our best to get your design on the run. If required, a waiting list will be created.

The TSMC run schedule for the second half of 2024 will be published later this year. We will share it with you as soon as it is available.

Bumping is available upon request for all 12-inch technologies.

Contact eptsmc@imec.be if any of the following options are used: Bumping, MTP/OTP, Deep Trench, High Linearity MiM, Schottky Barrier Diode, ULL N/PMOS.

Prices for TSMC technologies can be calculated through the online Price Request Form:

Exceptionally, prices for the TSMC University FinFET Program can be found here:

When 4 or more independent sub-designs are registered in one MPW submission to optimise the minimum charged area, an additional verification charge of 1,000 USD is applicable. This is regardless of the request and charges for sub die sawing (6 USD per additional die obtained from the base MPW submission).

TSMC mini@sic	Jan	Feb	Mar	Apr	May	Jun	Jul	Aug	Sep	Oct	Nov	Dec
TSMC 0.13µm CMOS BCD plus					1					30
TSMC 65nm CMOS Low Power MS/RF		21		17		19		21		16		11
TSMC 65nm CMOS GP MS/RF									11
TSMC 40nm CMOS Low Power MS/RF	31								18
TSMC 28nm CMOS RF HPC+	31			24			24			23
TSMC 16nm CMOS RF FinFET Compact			27								20

Important notes:

Dates are GDS submission deadlines.

Please check additional technology options for TSMC mini@sic:

Please check additional technology options for the TSMC University FinFET Program:

TSMC mini@sic Pricelist	Standard prices		Discounted prices
	EUR / min area	EUR / extra area	EUR / min area	EUR / extra area
TSMC 130 BCD+ (min area = 6 mm²)	13,982	231 / 0.1 mm²	12,482	190 / 0.1 mm²
TSMC 65 LP/GP MS RF (min area = 1 mm²)	4,462	418 / 0.1 mm²	3,662	358 / 0.1 mm²
TSMC 40 LP MS RF (min area = 3 mm²) ¹	21,249	662 / 0.1 mm²	18,249	599 / 0.1 mm²
TSMC 28 HPC+ RF (min area = 1 mm²) ¹	10,541	915 / 0.1 mm²	8,441	830 / 0.1 mm²
TSMC 16 FFC RF (min area = 1mm²) ^{2, 3}	30,364	2,814 / 0.1 mm²	26,364	2,557 / 0.1 mm²

Important notes:

The prices are area based, and the aspect ratio is free to choose but it is strongly recommended not to have sides less than 1mm.
Subdicing is not supported on mini@sic.
Design registration must be done at least 3 months in advance, preferably at the moment of reservation.

¹ The areas in the table for 28nm and 40nm are on-silicon dimensions. This means the designed area can be (area/0.81).

²The areas in the table for 16nm indicates on-silicon dimensions. This means the designed area can be (area/0.9604).

Please check additional technology options for TSMC mini@sic:

³ Prices and technology options for the TSMC University FinFET Program can be found here:

UMC MPW	Jan	Feb	Mar	Apr	Jun	Jul	Aug	Sep	Nov
UMC 28N Logic/Mixed-Mode – HPC		19		22		22
UMC 40N Logic/Mixed-Mode – LP			11		24	29	26		18
UMC 65N Logic/Mixed-Mode/RF – LL	2	26						2
UMC L110AE Logic/Mixed-Mode/RF		26			3			2
UMC L180 Logic GII, Mixed-Mode/RF			4				26

Important notes: Dates are GDS submission deadlines. Design registration must be done at least 3 weeks in advance.

Additional technology options are available:

UMC MPW Pricelist	Standard EUR / block	Discounted EUR / block
UMC L180 Logic GII, Mixed-Mode/RF	19,000 ¹	18,060 ¹
UMC L110AE Logic/Mixed-Mode/RF	34,800 ¹	33,060¹
UMC L65nm Logic, Mixed-Mode/ RF – LL/SP	50,600 ²	48,080 ²
UMC 40N Logic/Mixed-Mode – LP	98,050 ²	93,160 ²
UMC 28N Logic/ Mixed-Mode – HPC	On request. Please, contact epumc@imec.be

Important notes:

¹ Price = per block of 5mm x 5mm needed to fit the design in.
² Price = per block of 4mm x 4mm needed to fit the design in.

UMC mini@sic	Feb	Mar	Aug
UMC 65N Logic/Mixed-Mode/RF – LL	19		26
UMC L110AE Mixed-Mode/RF		4	26
UMC L180 Mixed-Mode/RF	26		19

Important notes: Dates are GDS submission deadlines. Design registration must be done at least 3 weeks in advance.

Additional technology options are available:

UMC mini@sic Pricelist	Standard EUR / block	Discounted EUR / block
UMC L180 Mixed-Mode/RF – 1P6M – 1.8V/3.3V *	4,110 ¹	3,430 ¹
UMC L110AE Logic/Mixed-Mode/RF **	8,920 ²	8,070 ²
UMC L65N Logic/Mixed-Mode LL ***	12,970 ³	11,720 ³

Important notes:

¹ Price = per block of 1525μm x 1525μm needed to fit the design in. Adding two blocks together to one block is possible.

² Price = per block of 2425μm x 1525μm needed to fit the design in.

³ Price = per block of 1875μm x 1875μm needed to fit the design in. Adding two blocks together to one block is possible.

* UMC 0.18μm mini@sic rules

When the standard block of 5mm x 5mm is divided into 9 regular square sub-blocks, customers participating in the mini@sic program can submit one sub-block or multiple sub-blocks, depending on the size of their design:

single sub-block: design may not be larger than 1525μm x 1525μm
2 sub-blocks: design may not be larger than 3240μm x 1525μm
3 sub-blocks: design may not be larger than 4960μm x 1525μm
4 sub-blocks: design may not be larger than 3240μm x 3240μm
6 sub-blocks: design may not be larger than 4960μm x 3240μm

Final price = number of sub-blocks needed to fit in the design * sub-block price.

** UMC 0.11μm mini@sic rules

single sub-block: design may not be larger than 2425μm x 1525μm
2 sub blocks: design may not be larger than 2425μm x 3140μm

*** UMC 65nm mini@sic rules

For the mini@sic program, customers can submit one sub-block or multiple sub-blocks, depending on the size of their design:

single sub-block: design may not be larger than 1875μm x 1875μm
2 sub-blocks: design may not be larger than 3950μm x 1875μm

UMS	Mar	May	Jul	Sep	Nov	Dec
UMS GH25\|GaN HEMT	22			20
UMS GH15\|GaN HEMT		24			22
UMS PH10\|GaAs pHEMT			19			13

Important notes: Dates are GDS submission deadlines. Design registration must be done at least 4 weeks in advance.

UMS may postpone the run depends on the cummalative chip area. At the area less than 10 mm² the run will be started in consultation with UMS. Wafer size: 4″

UMS Pricelist	Standard EUR / mm²	Discount EUR / mm²
UMS GH15\|GaN HEMT ¹	3,600	3,240
UMS GH25\|GaN HEMT ¹	3,400	3,060
UMS PH10\|GaAs pHEMT ²	2,300	2,070

Important notes:
¹Max. possible die area: 16 mm², available final X & Y dimension (mm): 1, 2, 3, 4, after fabrication and dicing.

Max. ratio X x Y dimension: 1:4. The customer Tape In area can be flexible and will be cut off according to the next possible manufactured chip size.

Die size includes 100 µm dicing street without inspection and test.

Delivery quantity: 16 dies in gel pack.

²Max. possible die area: 16 mm², available final X & Y sizes (mm): 1, 1.4, 2.4, 3.4, 4, after fabrication and dicing.

Max. ratio X x Y dimension: 1:3. The customer Tape In area can be flexible and will be cut off according to the next possible manufactured chip size.

Die size includes. 70 µm dicing street without inspection and test.

Delivery quantity 20 dies in gel pack.

Min fabrication cost equivalent to 3 mm².

X-FAB MPW	Jan	Feb	Mar	Apr	May	Jun	Jul	Aug	Sep	Oct	Nov
XT011 0.11µ HV SOI CMOS			11		6			26			18
XR013 0.13µ RF SOI CMOS *		12						12
XR013 0.13µ XIPD					13						4
XH018 0.18µ HV NVM CMOS E-FLASH	5		25			24				7
XP018 0.18µ NVM CMOS *	29				27				16
XT018 0.18µ HV SOI CMOS		26		22				12			4
XS018 0.18µ OPTO *		5					8
XH035 0.35µ HV CMOS			4					5			4
XMB10 MEMS									16

Important notes: Dates are GDS submission deadlines. Registration should be done at least 2 weeks in advance.

* In case of cancellation, there is a possibility to order these technologies by MLM.

Please take a look at additional technology options:

X-FAB MPW Pricelist	Standard EUR / mm²	Discounted EUR / mm²
XT011 0.11µ HV SOI CMOS (MOS5, MOSLP, DTI, PSUB, METAL1, METAL2, METAL3, METAL4, METAL5, COPTHK, ALUCAP)	2,300	2,190
XR013 0.13μ CMOS XIPD (XIPD, METTHK1, METRB, MIM, PIMIDE, BUMP, METBQSL)	845	805
XR013 0.13μ RF SOI CMOS (METRB, METBQ)	2,325	2,210
XR013 0.13μ RF SOI CMOS (METTHK1, METRB, METRQ)	2,895	2,750
XH018 0.18μ HV NVM CMOS E-FLASH (MET3, MET4, METMID, MET-THK)	2,025	1,925
XP018 0.18μ NVM CMOS (MET3, MET4, METMID, METTHK)	1,785	1,695
XT018 0.18μ HV SOI CMOS (MET3, MET4, METMID, METTHK)	2,040	1,940
XS018 0.18μ OPTO (MET3, MET4, MET5, METMID, MRPOLY, LVTN3D, BCH, MIMH, PPDB, 4TPIX, SFLATPV, ISOMOSA, MOS3LPPD)	1,495	1,420
XH035 0.35μ HV CMOS (MET4)	1,250	1,185
XMB10 MEMS	1,208 ¹	1,123 ¹

Important notes:

Price = area (mm²) * price/mm² with min. fabrication cost equivalent to 10mm².
Area will be rounded upwards to the next mm² (for instance, 12.24mm² will be charged as 13mm²).
Backgrinding (necessary for packaging) is not always possible and an additional cost might apply.

Delivery of 50 dies is included. Purchasing additional dies is not always possible and an additional cost may apply.

¹ Delivery of 5 dies is included. Additional dies can be purchased for 10EUR/die (50 dies maximum).

X-FAB mini@sic		Jan	Feb	Mar	Apr	May	Jun	Jul	Aug	Sep	Oct	Nov	Dec
XH018 0.18µ HV NVM CMOS E-FLASH				25							7
XT018 0.18µ HV SOI CMOS					22							4

Important notes: Dates are GDS submission deadlines. Registration should be done at least 2 weeks in advance.

Please take a look at additional technology options:

X-FAB mini@sic Pricelist		Standard EUR / block	Discounted EUR / block
X-FAB XH018 0.18μ HV NVM CMOS E-FLASH (MET3, MET4, METMID, MET-THK)		5,700	5,300
X-FAB XT018 0.18μ HV SOI CMOS (MET3, MET4, METMID, METTHK)		5,800	5,400

Important notes:

Price = per block of 1520μm x 1520μm needed to fit the design in. Adding two blocks together to one block is possible.
Backgrinding (necessary for packaging) is not always possible and an additional cost might apply.

Delivery of 50 dies is included. Purchasing additional dies is not always possible and an additional cost may apply.

AMF MPW		Jan	Feb	Mar	Apr	May	Jun	Jul	Aug	Sep	Oct	Nov	Dec
Si-Photonics fabrication process AMF						20					14

Important notes: For registration, please contact cime-prototypage@grenoble-inp.fr

CORNERSTONE MPW	Jan	Feb	Mar	Apr	May	Jun	Jul	Aug	Sep	Oct	Nov	Dec
CORNERSTONE Si-Photonics: 220 nm SOI passives		21			29						27
CORNERSTONE Si-Photonics: 220 nm SOI actives						26
CORNERSTONE Si-Photonics: 340 nm SOI passives			27						25
CORNERSTONE Si-Photonics: 500 nm SOI passives								28
CORNERSTONE SiN-Photonics	3						24					18
CORNERSTONE Si-Photonics: Suspended-Si				24						23
CORNERSTONE Ge-on-Si				24						23

Important notes: Dates are GDS submission deadlines. Registration should be done at least 4 weeks in advance.

CORNERSTONE MPW Pricelist	Standard EUR	Discounted EUR
Full block – Passives only, all SOI platforms (11.47mm x 4.9mm)	11,350	10,783
Half block – Passives only, all SOI platforms (5.5mm x 4.9mm)	7,870	7,477
Full block – Passives with heaters, all SOI platforms (11.47mm x 4.9mm)	17,950	17,053
Half block – Passives with heaters, all SOI platforms (5.5mm x 4.9mm)	13,220	12,559
Full block – Actives, 220nm SOI platform (11.47mm x 4.9mm)	61,300	58,235
Half block – Actives, 220nm SOI platform (5.5mm x 4.9mm)	36,800	34,960
Actives, 220nm SOI platform (2.5mm x 4.9mm)	18,860	17,917
Actives, 220nm SOI platform (2.5mm x 2.5mm)	10,060	9,557
SiN full block – SiN platform with heaters (11.47mm x 15.45mm)	17,950	17,053
SiN full block – SiN platform, passive (11.47mm x 15.45mm)	9,750	9,263
Suspended-Si full block (11.47mm x 4.9mm)	13,850	13,158
Suspended-Si half block (5.5mm x 4.9mm)	9,750	9,263
Ge-on-Si (15.45mm x 11.47mm)	13,850	13,158
Extra Options
Extra set of blocks – Passives (10 samples)	+2,200	+2,200
Extra set of blocks – Passives with heaters (10 samples)	+3,000	+3,000
Extra set of blocks – Actives (10 samples)	+5,000	+5,000

Important notes:

These prices are indicative and depend on the pound-to-euro exchange rate.

Standard number of samples for all platforms is 10. If more prototypes are needed, please see Extra Options in the table above.

Graphenea MPW	Feb	Apr	Jun	Aug	Oct	Dec
Graphenea Process Flow 1 – General	7			7
Graphenea Process Flow 2 – Biosensing		3			2
Graphenea Process Flow 3 – HKMG			5			4

Important notes: Dates indicate deadlines for submission of the first version of the GDS file.
Design registration should be done at least 4 weeks in advance.

Graphenea MPW Pricelist	Standard EUR	Discounted EUR
Process Flow 1 – General (4cm²)	1,200	1,140
Process Flow 2 – Biosensing (4cm²)	1,800	1,710
Process Flow 3 – HKMG (4cm²)	3,000	2,850
Extra Options
Extra die Process Flow 1 – General (per cm²)	850	808
Extra die Process Flow 2 – Biosensing (per cm²)	900	855
Extra die Process Flow 3 – HKMG (per cm²)	1,200	1,140

Important notes:

Minimum fabrication cost equivalent of 4 cm².

Die sizes can be either 10x10mm² or 5x5mm². All the dies must have the same size.

Not limited to a single design/reticle. Each die can have a different design.

imec MPW	Mar	May	Jun	Sep
imec Si-Photonics Passives+			5
imec Si-Photonics iSiPP50G	20			18
imec GaN-IC on SOI 200V		22
GaN-IC on SOI 650V				18

Important notes: Dates indicate deadlines for submission of the first version of the GDS file.
Design registration should be done at least 4 weeks in advance.

Admin. procedure must be finished at least 1 week before the dates indicated in the table.

imec MPW Pricelist Si-Photonics Passives+ ^{1, 2}	Standard EUR	Discounted EUR
Half block – horizontal (5.15mm x 2.5mm) or vertical (2.5mm x 5.15mm)	6,700	6,400
1 block (5.15mm x 5.15mm)	12,800	12,100
2 blocks – horizontal (10.45mm x 5.15mm) or vertical (5.15mm x 10.45mm)	22,700	21,500
4 blocks (10.45mm x 10.45mm)	44,000	42,000
Larger sizes	Please, contact epsiphot@imec.be
Extra Options
Extra set of half block chips (10 samples)	+2,500	+2,200
Extra set of chips (1 block or larger; 20 samples)	+2,500	+2,200
Si-Photonics iSiPP50G ^{1, 2}
Quarter block (2.5mm x 2.5mm)	11,000	10,500
Half block – horizontal (5.15mm x 2.5mm) or vertical (2.5mm x 5.15mm)	22,000	21,000
1 block (5.15mm x 5.15mm)	44,000	42,000
2 blocks – horizontal (10.45mm x 5.15mm) or vertical (5.15mm x 10.45mm)	88,000	83,500
4 blocks (10.45mm x 10.45mm)	165,000	157,000
Larger sizes	Please, contact epsiphot@imec.be
Extra Options
Extra set of quarter block chips (10 samples)	+2,500	+2,200
Extra set of half block chips (10 samples)	+2,500	+2,200
Extra set of chips (1 block or larger; 20 samples)	+2,500	+2,200

Important notes:

¹ There is a new process for the waveguides. Existing users, please be cautious.

² Number of prototypes in standard order depends on design size: 20 for 1 block or larger, 10 for half block or smaller.
Because of typical MPW logistics, we may sometimes deliver more chips than ordered.

imec MPW Pricelist GaN-IC on SOI 200V and 650V	Standard EUR	Discounted EUR
Half block (2.5mm x 5.18mm) *	22,000	20,240
Standard block (5.18mm x 5.18mm)	44,000	40,480
Double block (10.54mm x 5.18mm)	88,000	80,960
Extra Options
Extra set of chips (40 samples)	+5,000	+5,000
Sub-dicing **	+1,000	+1,000

Important notes: Regular number of samples is 40 .
Due to the nature of MPW logistics, more chips than ordered may sometimes be shipped.
* This option is only available to academic institutions.

** Per additional dicing lane, following MPW templates only. Sub-dicing options must be approved by the technical team. Please contact ganmpw@imec-int.com in advance to evaluate your request.

LioniX MPW	Mar	Jul	Oct	Nov	Dec
LNX SiN-Photonics TriPleX VIS	31		15
LNX SiN-Photonics TriPleX 1550	31	31		15
LNX SiN-Photonics TriPleX 850		15			29

Important notes:

Dates are GDS submission deadlines. For registration dates and other details, please contact marc.rensing@tyndall.ie

TBD * – The exact dates in June for TriPleX VIS and in September for TriPleX 850 are to be defined.

LioniX MPW Pricelist SiN-Photonics TriPleX		Standard EUR	Discounted EUR
4 samples of 10mm x 10mm		19,900	12,900¹
4 samples of 10mm x 20mm		29,900	19,000¹

Important notes:

For academic customers, the discount on the device manufacturing is offered on the condition that LioniX International will be co-author or acknowledged in the publications related to these devices.

Pragmatic MPW		Jan	Feb	Mar	Apr	May	Jun	Jul	Aug	Sep	Oct	Nov	Dec
Helvellyn				6		22				25

Important notes:

Dates indicate deadlines for submission of the first version of the GDS file. Design registration should be done at least 4 weeks in advance.

Full-wafer runs are possible on demand. Please contact flexicmpw@imec-int.com.

Pragmatic MPW Pricelist	Standard EUR / mm²	Discounted EUR / mm²
FlexIC Helvellyn ^{1, 2}	700	600
Extra Options
Additional set of 50 dies ³	500	500

Important notes:

¹ Price = area (mm²) * price/mm². Delivery quantity = 50 dies in gel-box.

² Minimum die size is 3mm x 3mm. Larger die sizes and other dimensions are also possible, but please first contact flexicmpw@imec-int.com before registration.

³Maximum 9 additional sets (450 additional dies) can be ordered. For more dies, please first contact flexicmpw@imec-int.com before registration.

For the full-wafer run pricelist, please contact flexicmpw@imec-int.com.

Science MPW	Jan	Feb	Mar	May	Jul	Sep	Oct
PolyMUMPs			20
SOIMUMPS		27			2		29
PiezoMUMPS	16			14		10

Important notes: Dates indicate deadlines for both Registration and submission of the first version of the GDS file.

Science MPW Pricelist		Standard EUR / block	Discounted EUR / block
PolyMUMPs (10mm x 10mm), SOIMUMPs (11 mm x 11mm), PiezoMUMPs (11mm x 11mm)		6,500	5000

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