SCHEDULES & PRICES

2024

Schedules 2025

2025 RUN SCHEDULES AND PRICES

On this page you can find General  MPW and mini@sic run schedules and prices for 2025.

If you need the 2024 schedules, please click here.

There are two prices in the EUROPRACTICE lists: Discounted and Standard.

 
DISCOUNTED PRICE

Three conditions should be met for Discounted prices:

  • Customer is an academic institution or a research facility from one of the 27 EU countries together with Albania, Armenia, Azerbaijan, Bosnia-Herzegovina, Georgia, Iceland, Israel, Liechtenstein, North Macedonia, Moldova, Montenegro, Norway, Switzerland, Turkey, Serbia, the UK and Ukraine.
  • Customer is a registered EUROPRACTICE member who has paid the Full-IC annual membership fee.
  • The intended design will be done for educational purposes or for publicly funded research.
 
STANDARD PRICE

Standard prices apply to all other customers.

To reserve your seat on a run, please register your design in the Registration Form or contact the EUROPRACTICE partner responsible for the technology.

ams OSRAM MPW
Jan
Feb
Mar
Apr
May
Jun
Jul
Aug
Sep
Oct
Nov
Dec
ams OSRAM 0.18µ CMOS atC18C6SH
6M/1P/HR/MIM/TW (Triple-well), 1.8V/3.3V
14
20
ams OSRAM 0.18µ CMOS
6M/1P/HR/MIM/TW (Triple-well), 1.8V/5.0V
20
ams OSRAM 0.35µ CMOS C35B4C3 4M/2P/HR/5V IO
24
14
3
ams OSRAM 0.35µ CMOS C35OPTO 4M/2P/5V IO
24
14
3
ams OSRAM 0.35µ HV CMOS H35B4D3 120V 4M/2P/HP
12
24
ams OSRAM 0.35µ HV CMOS OPTO 4M/2P/HP
12
24
Passive Interposer (TSV, RDL, Bumping)
6

Important notes: Dates are GDS submission deadlines. Design registration must be done at least 2 weeks in advance.

Dates in red are tentative runs.

Fraunhofer IISB
Jan
Feb
Mar
Apr
May
Jun
Jul
Aug
Sep
Oct
Nov
Dec
4H-SiC CMOS HIGH TEMPERATURE
7

Important notes: Dates are GDS submission deadlines. Design registration must be done at least 4 weeks in advance.

The first design submission (for our review and feedback) must be done on January 10, 2025. Fab-in: March 7, 2025.                                   

For new PDK download please ask virtual-asic@iis.fraunhofer.de

GLOBALFOUNDRIES MPW
Jan
Feb
Mar
Apr
May
Jun
Jul
Aug
Sep
Oct
Nov
Dec
GLOBALFOUNDRIES SiGe 8XP
4
2
8
GLOBALFOUNDRIES 130nm BCDlite – Gen2
1
8
31
GLOBALFOUNDRIES 55 nm BCDlite
10
16
8
25
GLOBALFOUNDRIES 45RFE
11
2
GLOBALFOUNDRIES 45nm RFSOI
7
8
GLOBALFOUNDRIES 45nm SPCLO – Silicon Photonics
8
19
10
GLOBALFOUNDRIES 28 nm SLPe
27
26
8
GLOBALFOUNDRIES 22 nm FDSOI
13
3
20
8
4
30
15
GLOBALFOUNDRIES 12 nm LP+
12
11
10

Important notes: Dates are Registration deadlines after which designs cannot be accepted.

Final GDSII file must be submitted within 6 weeks after this date.

Dates in red are preliminary.

cancellation fee is applicable if the registration is cancelled later than 2 weeks after the Registration deadline or if the customer is unable to provide a DRC-clean GDS before the Tapeout deadline.

IHP MPW
Jan
Feb
Mar
Apr
May
Jun
Jul
Aug
Sep
Oct
Nov
Dec
IHP SG13C SiGe:C RF CMOS
28
11
10
IHP SG13G2 SiGe:C Bipolar/Analog
28
11
10
IHP SG13G2Cu (FEOL process SG13G2 + Cu BEOL option from X-FAB)
24
11
10
IHP SG13G3Cu (FEOL process + Cu BEOL option from X-FAB)
24
11
10
IHP SG13G3 (FEOL process SG13G3Cu + Al-BEOL option)*
11
10
IHP SG13S SiGe:C Bipolar/Analog
28
11
10
IHP SG13SCu (FEOL process SG13S + Cu BEOL option from X-FAB)
24
10
IHP MEMRES for SG13S
28
10
IHP BEOL SG13 (M1 and Metal Layers Above) + optional LBE or TSV
7
Open-Source IHP SG13G2 SiGe:C Bipolar/Analog
31
Open-Source IHP SG13 CMOS
18
IHP SG13_Interposer Bipolar/Analog 7M
14
IHP SG25H5_EPIC high performance BiCMOS + Photonic
6

Important notes: 

Dates are Registration and Export Control information deadlines. Please download the Export Control file here.

Final GDSII file must be submitted within 10 calendar days after this date.

Final chip area incl. Sealring_complete must be provided 7 calendar days after the regsitration

The final chip area may not deviate by more than 5% from the registered area including the sealring.

Chip thickness different from 300µm or 200µm require extra fee.

 

MEMRES is available for IHP SG13S technology with extra charge.

TSV is available for IHP SG13S and SG13G2 technologies with extra charge.

Cu Pillar and Bumping are available for all IHP technologies with extra charge; SG13C on request.

Local Backside Etching (LBE) is not offered for EPIC runs and runs with Cu-BEOL.

 

* For research and prototyping purposes only.

 
 
TSMC MPW
Jan
Feb
Mar
Apr
May
Jun
Jul
Aug
Sep
Oct
Nov
Dec
TSMC 0.13µm CMOS BCD plus (12-inch)
29
7
23
5
TSMC 0.13µm CMOS Logic or MS/RF, GP or LP (12-inch)
29
7
23
5
TSMC 90nm CMOS Logic or MS/RF, GP or LP
11
10
TSMC 65nm CMOS Logic or MS/RF, GP or LP
5
2
21
27
22
TSMC 40nm CMOS Logic or MS/RF, LP
(no triple gate oxide)
5
5
2
23
28
23
27
24
22
19
TSMC 40nm CMOS Logic or MS/RF, GP
(no triple gate oxide)
5
23
27
TSMC 28nm CMOS Logic or RF HPC/HPC+
5
12
23
28
2
30
3
29
26
TSMC 22nm CMOS Logic or RF ULL
19
26
23
25
20
1
22
TSMC 16nm CMOS Logic or RF FinFET Compact
5
2
28
23
1
26
TSMC 7nm CMOS Logic or RF FinFET
Run planned for 18 December 2024
H2 2025 dates will be known at the end of March

Important notes:

Dates are GDS submission deadlines.

Several TSMC shuttles are extremely loaded. For any technology, please make your design registration as early as possible. We will work with you and do our best to get your design on the run. If required, a waiting list will be created.

 

Bumping is available upon request for all 12-inch technologies.

Contact eptsmc@imec.be if any of the following options are used: Bumping, MTP/OTP.

UMC MPW
Jan
Feb
Mar
Apr
May
Jun
Jul
Aug
Sep
Oct
Nov
Dec
UMC 28N Logic/Mixed-Mode – HPC
3
12
4
10
UMC 40N Logic/Mixed-Mode – LP
17
31
4
1
UMC 65N Logic/Mixed-Mode/RF – LL
14
30
29
UMC L110AE Logic/Mixed-Mode/RF
31
2
1
UMC L180 Logic GII, Mixed-Mode/RF
7
29

Important notes: Dates are GDS submission deadlines. Design registration must be done at least 4 weeks in advance.

Additional technology options are available:

UMS
Jan
Feb
Mar
Apr
May
Jun
Jul
Aug
Sep
Oct
Nov
Dec
UMS GH25|GaN HEMT
17
15
UMS GH15|GaN HEMT
19
17
UMS PH10|GaAs pHEMT
24
18

Important notes: Dates are GDS submission deadlines. Design registration must be done at least 4 weeks in advance.

Please fill in the Export Control questionnaire when registering your design and return it to virtual-asic@iis.fraunhofer.de

UMS may postpone the run depends on the cummalative chip area. At the area less than 10 mm² the run will be started in consultation with UMS. Wafer size: 4″

X-FAB MPW
Jan
Feb
Mar
Apr
May
Jun
Jul
Aug
Sep
Oct
Nov
Dec
XT011 0.11µ HV SOI CMOS
24
5
18
27
XR013 0.13µ RF SOI CMOS *
7
4
27
XR013 0.13µ XIPD
7
4
27
XH018 0.18µ HV NVM CMOS E-FLASH
13
24
23
6
XP018 0.18µ NVM CMOS *
3
2
15
XT018 0.18µ HV SOI CMOS
3
21
4
3
XS018 0.18µ OPTO *
10
30
XH035 0.35µ HV CMOS
3
4
3
XMB10 MEMS
15

Important notes: Dates are GDS submission deadlines. Registration should be done at least 4 weeks in advance.

* In case of cancellation, there is a possibility to order these technologies by MLM.

Please take a look at additional technology options:

imec MPW
Jan
Feb
Mar
Apr
May
Jun
Jul
Aug
Sep
Oct
Nov
Dec
imec Si-Photonics Passives+
4
imec Si-Photonics iSiPP50G
12
17
imec GaN-IC on SOI 100V
4
GaN-IC on SOI 650V
1

Important notes: Dates indicate deadlines for submission of the first version of the GDS file.
Design registration should be done at least 4 weeks in advance.

Admin. procedure must be finished at least 1 week before the dates indicated in the table.

Pragmatic MPW
Jan
Feb
Mar
Apr
May
Jun
Jul
Aug
Sep
Oct
Nov
Dec
Helvellyn
3

Important notes:

The calendar for more MPW runs in 2025 will be published soon.

Dates indicate deadlines for submission of the first version of the GDS file. Design registration should be done at least 4 weeks in advance.

Full-wafer runs are possible on demand. Please contact flexicmpw@imec-int.com.

Science MPW
Jan
Feb
Mar
Apr
May
Jun
Jul
Aug
Sep
Oct
Nov
Dec
PolyMUMPs
11
SOIMUMPS
26
2
29
PiezoMUMPS
14
30
3

Important notes: Dates are GDS submission deadlines. Design registration must be done at least 4 weeks in advance.

SINTEF PiezoMEMS
Jan
Feb
Mar
Apr
May
Jun
Jul
Aug
Sep
Oct
Nov
Dec
SINTEF PiezoMEMS
17
15

Important notes:

Dates indicate deadlines for submission of the first version of the GDS file. Design registration should be done at least 4 weeks in advance.