When working on the ASIC design, customers receive support from EUROPRACTICE with test insertion and ATPG (Automated Test Pattern Generation) to get the highest test coverage. Important know-how from the test house is used to improve the DFT (Design For Testability). As soon as a preliminary layout of the ASIC is ready, EUROPRACTICE can also provide technical support regarding the choice of package type and assembly requirements.
During the tape-out procedure, all circuits are checked against design rule violations with the “golden rule files” from the foundry. As a result, a correct GDS-II database is delivered to the foundry where the prototypes will be fabricated.
Together with Multi Project Wafer (MPW), EUROPRACTICE uses the Multi Layer Mask (MLM) technique to reduce fabrication costs.
In this case, the available mask area is typically divided in four quadrants (4L/R : four layer per reticle) whereby each quadrant is filled with one design layer. As an example, one mask can contain four layers such as nwell, poly, ndiff and active. The total number of masks is thus reduced by a factor of four. By adapting the lithographical procedure, it is possible to use one mask four times for the different layers by using the appropriate quadrants. Due to this technique, the mask costs can be reduced by approximately 60%.
These are some of the advantages of a MLM run:
The MLM technique is preferred over MPW runs when the chip area becomes large and when the customer wants to get a higher number of prototypes. If the prototypes are successful, the mask set can be used under certain conditions for low volume production.
MLM runs are only available for technologies from ON Semiconductor, IHP, GLOBALFOUNDRIES and XFAB.