SCHEDULES & PRICES

2022

Schedules 2022

GENERAL MPW & MINI@SIC SCHEDULES - 2022

Here you can find General MPW and mini@sic run schedules and pricelists for 2022.

To reserve your seat on a run, please register your design in the Registration Form or contact the EUROPRACTICE partner responsible for the technology.

PRICELISTS - 2022

There are two prices in the EUROPRACTICE lists: Discounted and Standard.

 
DISCOUNTED PRICE

Three conditions should be met for Discounted prices:

  • Customer is an academic institution or a research facility from one of the 28 EU countries together with Albania, Armenia, Azerbaijan, Belarus, Bosnia-Herzegovina, Georgia, Iceland, Israel, Liechtenstein, North Macedonia, Moldova, Montenegro, Norway, Switzerland, Turkey, Serbia and Ukraine.
  • Customer is a registered EUROPRACTICE member who has paid the Full-IC annual membership fee.
  • The intended design will be done for educational purposes or for publicly funded research.
 
STANDARD PRICE

Standard prices apply to all other customers.

ams MPW
Jan
Feb
Mar
Apr
May
Jun
Jul
Aug
Sep
Oct
Nov
Dec
ams 0.35µ CMOS C35B4C3 4M/2P/HR/5V IO
21
27
24
ams 0.35µ CMOS C35OPTO 4M/2P/5V IO
21
27
24
ams 0.35µ HV CMOS H35B4D3 120V 4M
2
7
ams 0.35µ SiGe-BiCMOS S35D4M5 /
CMOS-RF C35B4M3 4M/4P Thick MET4 – MIM
7
26

Important notes: Dates are GDS submission deadlines. Design registration must be done at least 2 weeks in advance.

Dates in red are MPW runs on request.

GLOBALFOUNDRIES MPW
Jan
Feb
Mar
Apr
May
Jun
Jul
Aug
Sep
Oct
Nov
Dec
GLOBALFOUNDRIES SiGe 8XP
21
23
22
21
GLOBALFOUNDRIES 130nm BCDlite – Gen2
21
29
GLOBALFOUNDRIES 55 nm LPe-RF
20
GLOBALFOUNDRIES 45RFSOI
3
16
19
GLOBALFOUNDRIES 45nm SPCLO – Silicon Photonics
14
13
12
12
GLOBALFOUNDRIES 28 nm SLPe
9
8
GLOBALFOUNDRIES 22 nm FDSOI
10
7
2
4
5
1
GLOBALFOUNDRIES 12 nm LP+
10
11
11
7

Important notes: Dates are Registration deadlines after which designs cannot be accepted.

Final GDSII file must be submitted within 6 weeks after this date.

Dates in red are preliminary.

cancellation fee is applicable if the registration is cancelled later than 2 weeks after the Registration deadline or if the customer is unable to provide a DRC-clean GDS before the Tapeout deadline.

Fraunhofer IISB
Jan
Feb
Mar
Apr
May
Jun
Jul
Aug
Sep
Oct
Nov
Dec
4H-SiC CMOS HIGH TEMPERATURE
28

Important notes: Dates are GDS submission deadlines. Design registration must be done at least 4 weeks in advance.

IHP MPW
Jan
Feb
Mar
Apr
May
Jun
Jul
Aug
Sep
Oct
Nov
Dec
IHP SGB25V 0.25µ SiGe:C Bipolar/Analog, Ft/Fmax= 75/95GHz, 5M/MIM, breakdown voltages up to 7V
18
15
IHP SG25H3 0.25µ SiGe:C Bipolar/Analog, Ft/Fmax= 110/180GHz, 5M/MIM, breakdown voltages up to 7V
18
15
SG25H5_EPIC Bipolar/Analog, Ft/Fmax= 220/290GHz, 7M/MIM + Photonics
18
21
IHP SG13S SiGe:C Bipolar/Analog, Ft/Fmax= 250/340GHz, 7M/MIM + optional TSV
1
2
25
IHP SG13C SiGe:C CMOS 7M/MIM
1
2
25
IHP SG13G2 SiGe:C Bipolar/Analog, Ft/Fmax= 350/450GHz, 7M/MIM + optional TSV
1
2
25
IHP SG13G2Cu FEOL process SG13G2 together with Cu BEOL option
4
1 *
2
25
IHP SG13SCu FEOL process SG13S together with Cu BEOL option
4
1 *
2
25
IHP SG13S + MEMRES Module
1
25
IHP SG25 PIC (Photonics, Ge Photo-diode, BEOL)
29
IHP BEOL SG13 (M1 and Metal Layers Above) + optional LBE or TSV
25

Important notes: Dates are Registration deadlines. Final GDSII file must be submitted within 10 days after this date.

* Additional MPW runs offered only when the cumulative area > 10 mm².

MEMRES is available for the IHP SG13S technology with extra charge.

TSV is available for IHP SG13S and SG13G2 technologies with extra charge

Cu Pillar and Bumping are available for all IHP technologies with extra charge

Local Backside Etching (LBE) is not offered for EPIC runs and runs with Cu-BEOL

 
 
TSMC MPW
Jan
Feb
Mar
Apr
May
Jun
Jul
Aug
Sep
Oct
Nov
Dec
TSMC 0.18µm CMOS Logic or Mixed-Signal/RF, General Purpose
5
23
30
6
13
27
1
8
22
29
20
3
24
31
TSMC 0.18µm CMOS High Voltage BCD Gen 2
5
2
27
4
1
8
22
29
3
24
TSMC 0.13µm CMOS Logic or MS/RF, GP or LP (8-inch)
9
4
TSMC 0.13µm CMOS BCD plus (12-inch)
20
9
TSMC 0.13µm CMOS Logic or MS/RF, GP or LP (12-inch)
5
9
30
8
20
9
TSMC 90nm CMOS Logic or MS/RF, GP or LP
9
11
10
7
TSMC 65nm CMOS Logic or MS/RF, GP or LP
2
13
1
27
31
26
21
TSMC 40nm CMOS Logic or MS/RF, GP or LP (no triple gate oxide)
2
23
30
8
27
31
5
23
TSMC 28nm CMOS Logic or RF HPC/HPC+
23
27
6
7
30
14
TSMC 16nm CMOS Logic or RF FinFET Compact
2
6
25
27
21
23

Important notes:

Dates are GDS submission deadlines.

Several TSMC shuttles are extremely loaded. For any technology, please make your design registration as early as possible. We will work with you and do our best to get your design on the run. If required, a waiting list will be created.

 

Bumping is available upon request for all 12-inch technologies.

Contact eptsmc@imec.be if any of the following options are used: Bumping, MTP/OTP, Deep Trench, High Linearity MiM, Schottky Barrier Diode, ULL N/PMOS.

UMC MPW
Jan
Feb
Mar
Apr
May
Jun
Jul
Aug
Sep
Oct
Nov
Dec
UMC 28N Logic/Mixed-Mode – HPC
7
9
8
7
UMC 40N Logic/Mixed-Mode – LP
14
14
11
5
21
UMC 65N Logic/Mixed-Mode/RF – LL
3
7
16
18
31
5
UMC 55N Logic/Mixed-Mode/RF – SP
3
7
16
18
31
5
UMC L110AE Logic/Mixed-Mode/RF
28
25
27
22
24
5
UMC L130 Logic
25
24
UMC L130 Mixed-Mode/RF
25
24
UMC L180 Logic GII
31
2
1
31
UMC L180 Mixed-Mode/RF
31
2
1
31

Important notes: Dates are GDS submission deadlines. Design registration must be done at least 3 weeks in advance.

 

Additional technology options are available:

X-FAB MPW
Jan
Feb
Mar
Apr
May
Jun
Jul
Aug
Sep
Oct
Nov
Dec
XH018 0.18µ HV NVM CMOS E-FLASH
3
25
11
24
19
XT018 0.18µ HV SOI CMOS
21
13
15
7
XS018 0.18µ OPTO *
28
5
XP018 0.18µ NVM CMOS *
7
30
3
XH035 0.35µ HV CMOS
10
29
5
4
XR013 0.13µ RF SOI CMOS *
22
23
22
7
XMB10 MEMS
14

Important notes: Dates are GDS submission deadlines. Registration should be done at least 2 weeks in advance.

* In case of cancellation, there is a possibility to order these technologies by MLM.

 

Please take a look at additional technology options:

CORNERSTONE MPW
Jan
Feb
Mar
Apr
May
Jun
Jul
Aug
Sep
Oct
Nov
Dec
CORNERSTONE Si-Photonics: 220 nm SOI passives
25
30
CORNERSTONE Si-Photonics: 220 nm SOI actives
28
CORNERSTONE Si-Photonics: 340 nm SOI passives
7
CORNERSTONE Si-Photonics: 500 nm SOI passives
24
CORNERSTONE SiN-Photonics
7
24
23
CORNERSTONE Si-Photonics: Suspended-Si
25
29

Important notes: Dates are GDS submission deadlines. Registration should be done at least 4 weeks in advance.

imec MPW
Jan
Feb
Mar
Apr
May
Jun
Jul
Aug
Sep
Oct
Nov
Dec
imec Si-Photonics Passives+ 1
1
imec Si-Photonics iSiPP50G
9
5
imec SiN-Photonics BioPIX 300
3
31
imec GaN-IC on SOI 200V
22
imec GaN-IC on SOI 650V
19

Important notes: Dates indicate deadlines for both Registration and submission of the first version of the GDS file.

1 The Q4 2022’s Silicon Photonics Passives+ run will be shifted to January 2023

LioniX MPW
Jan
Feb
Mar
Apr
May
Jun
Jul
Aug
Sep
Oct
Nov
Dec
LNX SiN-Photonics TriPleX VIS
31
LNX SiN-Photonics TriPleX 1550
31
31
15
LNX SiN-Photonics TriPleX 850
7

Important notes:

Dates are GDS submission deadlines. For registration dates and other details, please contact europratice.gateway@tyndall.ie

TBD * – The exact dates in June for TriPleX VIS and in September for TriPleX 850 are to be defined.

MEMSCAP MPW
Jan
Feb
Mar
Apr
May
Jun
Jul
Aug
Sep
Oct
Nov
Dec
PolyMUMPs
15
26
SOIMUMPS
1
5
2
PiezoMUMPS
11
3
6

Important notes: Dates indicate deadlines for both Registration and submission of the first version of the GDS file.

Fraunhofer IZM
Jan
Feb
Mar
Apr
May
Jun
Jul
Aug
Sep
Oct
Nov
Dec
Fan-Out Wafer-Level Packaging (FOWLP)
11*
18**

Important notes: 

* FOWLP package design according Design Rules IZM (“Layout”): until April 11, 2022

Chips to be processed including 5 to 10 set-up chips: until May 27, 2022

 

** FOWLP package design according Design Rules IZM (“Layout”): until November 18, 2022

Chips to be processed including 5 to 10 set-up chips: until January 06, 2023