SCHEDULES & PRICES

2026

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Schedules 2026

2026 RUN SCHEDULES AND PRICES

On this page you can find General MPW and mini@sic run schedules and prices for 2026.

If you need the 2025 schedules, please click here.

There are two prices in the Europractice lists: Discounted and Standard.

DISCOUNTED PRICE

Three conditions should be met for Discounted prices:

Customer is an academic institution or a research facility from one of the 27 EU countries together with Albania, Armenia, Azerbaijan, Bosnia-Herzegovina, Georgia, Iceland, Israel, Liechtenstein, North Macedonia, Moldova, Montenegro, Norway, Switzerland, Turkey, Serbia, the UK and Ukraine.
Customer is a registered Europractice member who has paid the Full-IC annual membership fee.
The intended design will be done for educational purposes or for publicly funded research.

STANDARD PRICE

Standard prices apply to all other customers.

To reserve your seat on a run, please register your design in the Registration Form or contact the Europractice partner responsible for the technology.

ams OSRAM MPW	Mar	May	Jun	Jul	Oct	Nov
ams OSRAM 0.18µ CMOS at C18C6SG 6M/1P/HR/MIM/TW (Triple-well), 1.8V/3.3V			2		19
ams OSRAM 0.18µ CMOS 6M/1P/HR/MIM/TW (Triple-well), 1.8V/5.0V					19
ams OSRAM 0.35µ CMOS C35B4C3 4M/2P/HR/5V IO	23			13		2
ams OSRAM 0.35µ CMOS C35B4O1 4M/2P/HR/5V IO ARC photodiode in EPI layer	23			13		2
ams OSRAM 0.35µ HV CMOS H35B4D3 120V 4M/2P/HP		29				23
ams OSRAM 0.35µ HV CMOS OPTO 4M/2P/HP BARC photodiode in Epi layer		29				23
Passive Interposer (TSV, RDL, Bumping)	23					2

Important notes: Dates are GDS submission deadlines. Design Registration and Export Control must be done at least 2 weeks in advance. Please download and complete Export control and 21B file here.

ams OSRAM MPW Pricelist	Standard EUR / mm²	Discounted EUR / mm²
ams OSRAM 0.18µ CMOS atC18C6SH 6M/1P/HRP/TW (Triple-well), 1.8V/3.3V	1,650³	1,500³
ams OSRAM 0.35µ CMOS C35B4C3 4M/2P/HR/5V IO	640¹	580¹
ams OSRAM 0.35µ CMOS C35OPTO 4M/2P/5V	800²	700²
ams OSRAM 0.35µ HV CMOS H35B4D3 120V 4M	880¹	800¹

Important notes:

¹ Price = area (mm²) * price/mm² with min. fabrication cost equivalent to 10mm²

²Price = area (mm²) * price/mm²with min. fabrication cost equivalent to 20mm²

³Price = area (mm²) * price/mm²with min. fabrication cost equivalent to 5.5mm²

Fraunhofer IISB		Jan	Feb	Mar	Apr	May	Jun	Jul	Aug	Sep	Oct	Nov	Dec
4H-SiC CMOS HIGH TEMPERATURE					13

Important notes:

Dates are GDS submission deadlines. To participate in a process run, customers must have a valid NDA and register at least 4 weeks in advance. Please consult the latest PDK release for complete specifications and guidelines. For NDA, PDK download, and registration please contact silicon-asic@iis.fraunhofer.de .

Fraunhofer IISB Pricelist		Standard EUR / block	Discount EUR / block
4H-SiC CMOS HIGH TEMPERATURE (2.5mm x 5mm)¹		10,900	9,900
4H-SiC CMOS HIGH TEMPERATURE (5mm x 5mm)²		21,250	19,250

Important notes:
¹Max. design surface: 2.35mm x 4.85mm

²Max. design surface: 4.85mm x 4.85mm

Larger chip sizes and pricing are available on request.

GLOBALFOUNDRIES MPW	Jan	Feb	Mar	Apr	May	Jun	Jul	Aug	Sep	Oct	Dec
GLOBALFOUNDRIES SiGe 8XP			17					31
GLOBALFOUNDRIES 130nm BCDlite – Gen2		8						24
GLOBALFOUNDRIES 55 nm BCDlite			2			1		31
GLOBALFOUNDRIES 45RFE			10						14
GLOBALFOUNDRIES 45nm RFSOI		9					13
GLOBALFOUNDRIES 45nm SPCLO – Silicon Photonics				13				11			15
GLOBALFOUNDRIES 28 nm SLPe			2			1			7
GLOBALFOUNDRIES 22 nm FDSOI	27		16		4	30		17		5	5
GLOBALFOUNDRIES 12 nm LP+			26			25			10
GLOBALFOUNDRIES 180 MCU (open-source PDK)				26			19

Important notes: Dates are Registration deadlines after which designs cannot be accepted.

Final GDSII file must be submitted within 6 weeks after this date.

Dates in red are preliminary.

A cancellation fee is applicable if the registration is cancelled later than 2 weeks after the Registration deadline or if the customer is unable to provide a DRC-clean GDS before the Tapeout deadline.

GLOBALFOUNDRIES MPW Pricelist	Standard EUR / mm²	Discounted EUR / mm²
GLOBALFOUNDRIES SiGe 8XP	5,060 ¹	4,600 ¹
GLOBALFOUNDRIES 130 nm BCDlite	1,760 ¹	1,600 ¹
GLOBALFOUNDRIES 55 nm BCDlite	5,720 ²	5,200 ²
GLOBALFOUNDRIES 45RFE	10,230 ¹	9,300 ¹
GLOBALFOUNDRIES 45RFSOI	10,230 ¹	9,300 ¹
GLOBALFOUNDRIES 45nm SPCLO -Silicon Photonics (price per fixed block 5mm x 5mm)	242,000	220,000
GLOBALFOUNDRIES 28 nm SLPe	12,430 ³	11,300 ³
GLOBALFOUNDRIES 22 nm FDSOI	18,975 ³	17,250 ³
GLOBALFOUNDRIES 12 nm LP+	31,240 ³	28,400 ³
GLOBALFOUNDRIES 180 MCU (Open PDK)	913 ⁴	830 ⁴

Important notes:

¹ Price = area (mm²) * price/mm² with min. fabrication cost equivalent to 12 mm². Any edge length between 1.0 mm to 11 mm is possible. The mentioned die size is referred to the Pre-Shrink die size.

² Price = area (mm²) * price/mm² with min. fabrication cost equivalent to 9 mm². Any edge length between 1.0 mm to 11 mm is possible. The mentioned die size is referred to the Pre-Shrink die size.

³ Price = area (mm²) * price/mm² with min. fabrication cost equivalent to 4 mm². The mentioned die size is referred to the Pre-Shrink die size.

⁴ Price = area (mm²) * price/mm² with min. fabrication cost equivalent to 6 mm². The mentioned die size is referred to the Pre-Shrink die size.

GLOBALFOUNDRIES MPW	Jan	Feb	Mar	Apr	May	Jun	Jul	Aug	Sep	Oct	Dec
GLOBALFOUNDRIES SiGe 8XP			17					31
GLOBALFOUNDRIES 130nm BCDlite – Gen2		8						24
GLOBALFOUNDRIES 55 nm BCDlite			2			1		31
GLOBALFOUNDRIES 45RFE			10						14
GLOBALFOUNDRIES 45nm RFSOI		9					13
GLOBALFOUNDRIES 45nm SPCLO – Silicon Photonics				13				11			15
GLOBALFOUNDRIES 28 nm SLPe			2			1			7
GLOBALFOUNDRIES 22 nm FDSOI	27		16		4	30		17		5	5
GLOBALFOUNDRIES 12 nm LP+			26			25			10
GLOBALFOUNDRIES 180 MCU (open-source PDK)				26			19

Important notes:

The mini@sic model of GlobalFoundries is available only for universities and research institutes.

Dates are Registration deadlines after which designs cannot be accepted.

Final GDSII file must be submitted within 6 weeks after this date.

Dates in red are preliminary.

GLOBALFOUNDRIES mini@sic Pricelist	Standard EUR / mm²	Discounted EUR / mm²
GLOBALFOUNDRIES SiGe 8XP	7,260 ¹	6,600 ¹
GLOBALFOUNDRIES 130nm BCDlite – Gen2	3,080 ²	2,800 ²
GLOBALFOUNDRIES 55 nm BCDlite	8,250 ¹	7,500 ¹
GLOBALFOUNDRIES 45RFE	13,200 ¹	12,000 ¹
GLOBALFOUNDRIES 45RFSOI	13,200 ¹	12,000 ¹
GLOBALFOUNDRIES 45nm SPCLO -Silicon Photonics	154,000 ⁴	140,000 ⁴
GLOBALFOUNDRIES 28 nm SLPe	18,370 ³	16,700 ³
GLOBALFOUNDRIES 22 nm FDSOI	25,080 ³	22,800 ³
GLOBALFOUNDRIES 12 nm LP+	38,500 ³	35,000 ³

Important notes:

¹ Price = area (mm²) * price/mm² with min. fabrication cost equivalent to 2.5 mm². The mentioned die size is referred to the Pre-Shrink die size.

² Price = area (mm²) * price/mm² with min. fabrication cost equivalent to 5 mm². The mentioned die size is referred to the Pre-Shrink die size.

³ Price = area (mm²) * price/mm² with min. fabrication cost equivalent to 1 mm².The mentioned die size is referred to the Pre-Shrink die size.

⁴ Price = fixed block size of 5mm x 2.455mm or 2.455mm x 5mm.

IHP MPW	Jan	Feb	Mar	May	Jun	Jul	Sep	Oct	Nov
SG25H7_EPIC A photonic BiCMOS technology								2
IHP SG13S SiGe:C Bipolar/Analog, Ft/Fmax= 250/340GHz, 7M/MIM, optional with TSV				1		31			6
IHP MEMRES (RRAM) fully CMOS integrated memristive module for SG13G2 technology				1					6
IHP SG13SCu FEOL process SG13S together with 8 layer Cu BEOL from X-FAB						31			6
IHP SG13CMOS SiGe:C includes all features of SG13G2 but not HBT			6*		19*			23*
IHP SG13CMOS5L SiGe:C A CMOS technology offered for open-source education designs, includes FEOL SG13CMOS			6*		19*			23*
IHP SG13G2 SiGe:C Bipolar/Analog, Ft/Fmax= 350/450GHz, 7M/MIM, optional with TSV				1		31			6
IHP SG13CMOS, includes all features of SG13G2 but not HBT, CMOS 7M/MIM, based on SG13G2 PDK				1		31			6
IHP SG13G2Cu FEOL process SG13G2 together with 8 layer Cu BEOL from X-FAB		13				31			6
IHP SG13G3 FEOL, the same FEOL process SG13G3Cu, with Al-BEOL option						31			6
IHP SG13G3Cu SiGe:C Bipolar/Analog, highest performance HBT’s, FEOL process with Cu BEOL from X-FAB		13				31			6
IHP SG25H7_PIC Incl. additional photonic design layers along with BiCMOS BEOL layers on SOI wafers	16
IHP BEOL SG13 (M1 and Metal Layers Above), optional TSV				15**
IHP INTM4TM2 Interposer technology, 2 thin and 2 thick Al-BEOL layer on a HRes substrate			16			27
IHP SG13G2 SiGe:C Bipolar/Analog, Ft/Fmax= 350/450GHz, 7M/MIM, optional with TSV							7*

Important notes:

Dates are Registration and Export Control information deadlines. Please download the Export Control file here.

Final GDSII file must be submitted within 10 calendar days after registration.

Final chip area incl. Sealring_complete must be provided 7 calendar days after the registration.

The final chip area may not deviate by more than 5% from the registered area including the sealring.

Standard wafer thickness 300 um. Another back lapping option is available on request.

As default 40 diced samples will be delivered. For designs using TSV module and SG25_H7PIC, 25 samples will be delivered by default.

MEMRES is available for IHP SG13G2 technology with extra charge.

TSV is available for IHP SG13S and SG13G2 technologies with extra charge.

Cu Pillar and Bumping are available for all IHP technologies with extra charge; SG13C on request.

Local Backside Etching (LBE) is not offered for EPIC runs and runs with Cu-BEOL.

* Low costs Open-Source MPW Runs with special conditions and signed Open Silicon MPW Program Participation Agreement is required. More details under the link Open Source Request

** BEOL plus TSV will be offered for max chip size 3 x 3 mm²

IHP MPW Pricelist	Standard EUR / mm²	Discounted EUR / mm²
SG25H7_EPIC A monolithic photonic BiCMOS technology	9,000 ^1,3	7,650 ^1,3
IHP SG13S SiGe:C Bipolar/Analog, HBT, CMOS, Ft/Fmax= 250/340GHz, 7M/MIM	6,300 ¹	5,355¹
IHP SG13SCu FEOL process SG13S together with 8 layer Cu BEOL from X-FAB	6,300 ¹	5,355 ¹
IHP SG13CMOS SiGe:C includes all features of SG13G2 but not HBT	4,500¹	3,825¹
IHP SG13G2 SiGe:C Bipolar/Analog, HBT, CMOS,Ft/Fmax= 350/450GHz	7,300¹	6,205 ¹
IHP SG13G2Cu FEOL process SG13G2 together with 8 layer Cu BEOL from X-FAB	7,300 ¹	6,205 ¹
IHP SG13G3 FEOL, the same FEOL process SG13G3Cu, with Al-BEOL option	9,000 ¹	7,650 ¹
IHP SG13G3Cu SiGe:C Bipolar/Analog, Ft/Fmax= 470/650GHz FEOL process with Cu BEOL from X-FAB	9,000 ¹	7,650 ¹
IHP SG25H7_PIC Incl. additional photonic design layers along with BiCMOS BEOL layers on SOI wafers.	4,500 ^1,3	3,825 ^1,3
IHP BEOL SG13 (M1 and Metal Layers Above)	1,300 ¹	1170 ¹
IHP INTM4TM2 Interposer technology, 2 thin and 2 thick Al-BEOL layer on a HRes substrate, MIM capacitor, Thin film Res.	900	765
IHP Special Services
Cu Pillar	on request²	on request²
Bumping (available for all IHP technologies), SG13C on request	on request²	on request²
Localized Back side Etching (available for IHP technologies with AL BEOL only), not offered for EPIC/PIC runs	5,000²	4,250 ²
TSV to ground (SG13S / G2)	12,500 ^2,3	10,625 ^2,3
MEMRES Module, CMOS integrated memristive module, on time fee offered for SG13G2	2,500²	2,000²
MEMRES Module additional fee per mm²	600¹	510¹
Price for Open Source Runs
SG13CMOS (closed source)	3,600	3,060
SG13G2 (closed source)	5,840	4,964
SG13CMOS & SG13CMOS5L(open source)	1,500⁴	1,500¹
SG13CMOS & SG13CMOS5L(open source)	1,000⁵	1,000⁵
SG13G2 (open source)	2,800⁴	2,800⁴

Important notes:

¹ Price = area (mm²) * price/mm² with min. fabrication cost equivalent to 0.8mm².
The chip area is inclusive of the filler cells outside the seal ring.
² One-off fee
³ Delivery quantity: 25 dies.

⁴ price is valid for cumulative area > 100 mm²
⁵ price is valid for cumulative area > 150 mm²

Fabrication of a chip area less than 0.8mm² and X & Y ratio larger than 1:3 is on request.

Standard MPW price is for designs created for educational purposes or publicly funded research for non-EU countries.

Discounted MPW price is meant for designs created for educational purposes or publicly funded research for non-EU countries.

IHP MPW	Jan	Feb	Mar	May	Jun	Jul	Sep	Oct	Nov
SG25H7_EPIC A photonic BiCMOS technology								2
IHP SG13S SiGe:C Bipolar/Analog, Ft/Fmax= 250/340GHz, 7M/MIM, optional with TSV				1		31			6
IHP MEMRES (RRAM) fully CMOS integrated memristive module for SG13G2 technology				1					6
IHP SG13SCu FEOL process SG13S together with 8 layer Cu BEOL from X-FAB						31			6
IHP SG13CMOS SiGe:C includes all features of SG13G2 but not HBT			6*		19*			23*
IHP SG13CMOS5L SiGe:C A CMOS technology offered for open-source education designs, includes FEOL SG13CMOS			6*		19*			23*
IHP SG13G2 SiGe:C Bipolar/Analog, Ft/Fmax= 350/450GHz, 7M/MIM, optional with TSV				1		31			6
IHP SG13CMOS, includes all features of SG13G2 but not HBT, CMOS 7M/MIM, based on SG13G2 PDK				1		31			6
IHP SG13G2Cu FEOL process SG13G2 together with 8 layer Cu BEOL from X-FAB		13				31			6
IHP SG13G3 FEOL, the same FEOL process SG13G3Cu, with Al-BEOL option						31			6
IHP SG13G3Cu SiGe:C Bipolar/Analog, highest performance HBT’s, FEOL process with Cu BEOL from X-FAB		13				31			6
IHP SG25H7_PIC Incl. additional photonic design layers along with BiCMOS BEOL layers on SOI wafers	16
IHP BEOL SG13 (M1 and Metal Layers Above), optional TSV				15**
IHP INTM4TM2 Interposer technology, 2 thin and 2 thick Al-BEOL layer on a HRes substrate			16			27
IHP SG13G2 SiGe:C Bipolar/Analog, Ft/Fmax= 350/450GHz, 7M/MIM, optional with TSV							7*

Important notes:

Dates are Registration and Export Control information deadlines. Please download the Export Control file here.

Final GDSII file must be submitted within 10 calendar days after registration.

Final chip area incl. Sealring_complete must be provided 7 calendar days after the registration.

The final chip area may not deviate by more than 5% from the registered area including the sealring.

Standard wafer thickness 300 um. Another back lapping option is available on request.

As default 40 diced samples will be delivered. For designs using TSV module and SG25_H7PIC, 25 samples will be
delivered by default.

MEMRES is available for IHP SG13G2 technology with extra charge.

TSV is available for IHP SG13S and SG13G2 technologies with extra charge.

Cu Pillar and Bumping are available for all IHP technologies with extra charge; SG13C on request.

Local Backside Etching (LBE) is not offered for EPIC runs and runs with Cu-BEOL.

* Low costs Open-Source MPW Runs with special conditions and signed Open Silicon MPW Program Participation Agreement is required. More details under the link Open Source Request

** BEOL plus TSV will be offered for max chip size 3 x 3 mm²

IHP MPW Pricelist	Standard EUR / mm²	Discounted EUR / mm²
SG25H7_EPIC A monolithic photonic BiCMOS technology	7,650^1,3	6,750 ^1,3
IHP SG13S SiGe:C Bipolar/Analog, HBT, CMOS, Ft/Fmax= 250/340GHz, 7M/MIM	5,355 ¹	4,410¹
IHP SG13SCu FEOL process SG13S together with 8 layer Cu BEOL from X-FAB	5,355 ¹	4,410 ¹
IHP SG13CMOS SiGe:C includes all features of SG13G2 but not HBT	3,825¹	3,600¹
IHP SG13G2 SiGe:C Bipolar/Analog, HBT, CMOS,Ft/Fmax= 350/450GHz	6,205¹	5,110 ¹
IHP SG13G2Cu FEOL process SG13G2 together with 8 layer Cu BEOL from X-FAB	6,205 ¹	5,110 ¹
IHP SG13G3 FEOL, the same FEOL process SG13G3Cu, with Al-BEOL option	7,650 ¹	6,300 ¹
IHP SG13G3Cu SiGe:C Bipolar/Analog, Ft/Fmax= 470/650GHz FEOL process with Cu BEOL from X-FAB	7,650 ¹	6,300 ¹
IHP SG25H7_PIC Incl. additional photonic design layers along with BiCMOS BEOL layers on SOI wafers.	3,825 ^1,3	3,600 ^1,3
IHP BEOL SG13 (M1 and Metal Layers Above)	1,170 ¹	1170 ¹
IHP INTM4TM2 Interposer technology, 2 thin and 2 thick Al-BEOL layer on a HRes substrate, MIM capacitor, Thin film Res.	765	720
IHP Special Services
Cu Pillar	on request²	on request²
Bumping (available for all IHP technologies), SG13C on request	on request²	on request²
Localized Back side Etching (available for IHP technologies with AL BEOL only), not offered for EPIC/PIC runs	4,250²	2,500 ²
TSV to ground (SG13S / G2)	10,625 ^2,3	7,500 ^2,3
MEMRES Module, CMOS integrated memristive module, on time fee offered for SG13G2	2,000²	2,000²
MEMRES Module additional fee per mm²	510¹	450¹
Price for Open Source Runs
SG13CMOS (closed source)	3,060	2,880
SG13G2 (closed source)	4,964	4,672
SG13CMOS & SG13CMOS5L(open source)	1,500⁴	1,500¹
SG13CMOS & SG13CMOS5L(open source)	1,000⁵	1,000⁵
SG13G2 (open source)	2,800⁴	2,800⁴

Important notes:

⁴ price is valid for cumulative area > 100 mm²
⁵ price is valid for cumulative area > 150 mm²

Fabrication of a chip area less than 0.8mm² and X & Y ratio larger than 1:3 is on request.

Standard MPW price is for designs created for educational purposes or publicly funded research for non-EU countries.

Discounted MPW price is meant for designs created for educational purposes or publicly funded research for non-EU countries.

STMicroelectronics MPW	Apr	May	Jun	Aug	Sep
ST BiCMOS55X	3			21
ST BiCMOS9MW		7
ST CMOS28FDSOI
ST HCMOS9A			5
ST P28					18

Important notes: Dates are GDS submission deadlines. Design registration has to be done at least 4 weeks in advance.

STMicroelectronics MPW Pricelist	Standard EUR / mm²	Additional area beyond X mm²	Discount EUR / project
ST BiCMOS55X	5,500	4,250²	1,200
ST BiCMOS9MW	3,500	2,950²	1,000
ST CMOS28FDSOI	9,000	6,750¹	1,500
ST HCMOS9A	3,550	3,150²	700
ST P28	12,150	9,100¹	1,500

Important notes:

All prices have a minimum charge of 1.25mm² including seal-ring.

Area = X*Y including seal-ring. The mentioned die size is referred to the Pre-Shrink die size.

Additional areas:

¹ Between 2 and 10 mm²

² Between 5 and 10 mm²

Reduced rate for additional mm² above 10mm²

TSMC MPW	Jan	Feb	Mar	Apr	May	Jun	Jul	Aug	Sep	Oct	Nov	Dec
TSMC 0.13µm CMOS BCD plus (12-inch)				12				16			15
TSMC 0.13µm CMOS Logic or MS/RF, GP or LP (12-inch)				12				16			15
TSMC 90nm CMOS Logic or MS/RF, GP or LP								16
TSMC 65nm CMOS Logic or MS/RF, GP or LP			8	19		14	19		13	18	15
TSMC 55nm CMOS Logic or MS/RF, GP or LP or ULP						14
TSMC 40nm CMOS Logic or MS/RF, LP (no triple gate oxide)	15	19		9	7	11		6	10	8		10
TSMC 40nm CMOS Logic or MS/RF, GP (no triple gate oxide)		19							10
TSMC 28nm CMOS Logic or RF HPC/HPC+		1	1		3 31			9	6		8	6
TSMC 22nm CMOS Logic or RF ULL (w/ or wo/ ReRam)			1	12	10	28		2 30			1 29
TSMC 16nm CMOS Logic or RF FinFET Compact	29			5	28			6		1	26
TSMC 7nm CMOS Logic or RF FinFET				5			*	*	*	*	*	*

Important notes:

Dates are final gds deadlines.
For a more detailed schedule please click on the “Detailed Submission Schedule” on top.

Several TSMC shuttles are extremely loaded. For any technology, please make your design registration as early as possible. We will work with you and do our best to get your design on the run. If required, a waiting list will be created.

* The schedule for the period July to December will be published on 16 March 2026.

Bumping is available upon request for all 12-inch technologies.

Please note that eFuse for 65 nm is only supported in Fab12. Please select the correct shuttle.

Contact eptsmc@imec.be if any of the following options are used: Bumping, MTP/OTP.

Prices for TSMC technologies can be calculated through the online Price Request Form:

Exceptionally, prices for the TSMC University FinFET Program can be found here:

When 4 or more independent sub-designs are registered in one MPW submission to optimise the minimum charged area, an additional verification charge of 1,000 USD is applicable. This is regardless of the request and charges for sub die sawing (6 USD per additional die obtained from the base MPW submission).

TSMC mini@sic	Feb	Mar	Apr	May	Jul	Sep	Oct	Nov
TSMC 0.13µm CMOS BCD plus		31						3
TSMC 65nm CMOS Low Power MS/RF	24		28		7	1		3
TSMC 65nm CMOS GP MS/RF			7				6
TSMC 40nm CMOS Low Power MS/RF		30				28
TSMC 28nm CMOS RF HPC+	17		21	19	28		27
TSMC 16nm CMOS RF FinFET Compact		24						16

Important notes:

Dates are final gds deadlines. For a more detailed schedule please click on the “Detailed Submission Schedule” on top.

* Please note that this date is tentative and may be adjusted.

Please check additional technology options for TSMC mini@sic:

Please check additional technology options for the TSMC University FinFET Program:

TSMC mini@sic Pricelist	Standard prices		Discounted prices
	EUR / min area	EUR / extra area	EUR / min area	EUR / extra area
TSMC 130 BCD+ (min area = 6 mm²)	14,054	232 / 0.1 mm²	12,554	191 / 0.1 mm²
TSMC 65 LP/GP MS RF (min area = 1 mm²)	4,491	419 / 0.1 mm²	3,691	360 / 0.1 mm²
TSMC 40 LP MS RF (min area = 3 mm²) ¹	21,386	664 / 0.1 mm²	18,386	602 / 0.1 mm²
TSMC 28 HPC+ RF (min area = 1 mm²) ¹	10,609	919.19 / 0.1 mm²	8,509	834 / 0.1 mm²
TSMC 16 FFC RF (min area = 1mm²) ^{2, 3}	30,592	2,826.96 / 0.1 mm²	26,592	2,568 / 0.1 mm²

Important notes:

The prices are area based, and the aspect ratio is free to choose but it is strongly recommended not to have sides less than 1mm.
Subdicing is not supported on mini@sic.
Design registration must be done at least 3 months in advance, preferably at the moment of reservation.

¹ The areas in the table for 28nm and 40nm are on-silicon dimensions. This means the designed area can be (area/0.81).

²The areas in the table for 16nm indicates on-silicon dimensions. This means the designed area can be (area/0.9604).

Please check additional technology options for TSMC mini@sic:

³ Prices and technology options for the TSMC University FinFET Program can be found here:

UMC MPW	Jan	Feb	Apr	May	Jul	Aug	Sep	Oct	Dec
UMC 28N Logic/Mixed-Mode – HPC	30			1	31			30
UMC 40N Logic/Mixed-Mode – LP			10			7		2	11
UMC 65N Logic/Mixed-Mode/RF – LL			17		17			9
UMC L110AE Logic/Mixed-Mode/RF		20		8	10		11		4
UMC L180 Logic GII, Mixed-Mode/RF			17					9

Important notes: Dates are GDS submission deadlines. Design registration must be done at least 4 weeks in advance.

Additional technology options are available:

UMC MPW Pricelist	Standard EUR / block	Discounted EUR / block
UMC L180 Logic GII, Mixed-Mode/RF	16,750 ¹	15,920 ¹
UMC L110AE Logic/Mixed-Mode/RF	24,300 ¹	23,100¹
UMC L65nm Logic, Mixed-Mode/ RF – LL/SP	43,750 ²	41,580 ²
UMC 40N Logic/Mixed-Mode – LP	70,500 ²	66,980 ²
UMC 28N Logic/ Mixed-Mode – HPC	On request. Please, contact epumc@imec.be

Important notes:

¹ Price = per block of 5mm x 5mm needed to fit the design in.
² Price = per block of 4mm x 4mm needed to fit the design in.

When four or more independent sub-designs are registered in one MPW submission to optimize the minimum charged area, an additional verification charge of 1,000 EUR will be applied.

UMC mini@sic		Jan	Feb	Mar	Apr	May	Jun	Jul	Aug	Sep	Oct	Nov	Dec
UMC L180 Mixed-Mode/RF				30						21

Important notes: Dates are GDS submission deadlines. Design registration must be done at least 4 weeks in advance.

Additional technology options are available:

UMC mini@sic Pricelist		Standard EUR / block	Discounted EUR / block
UMC L180 Mixed-Mode/RF – 1P6M – 1.8V/3.3V *		4,110 ¹	3,430 ¹

Important notes:

¹ Price = per block of 1525μm x 1525μm needed to fit the design in. Adding two blocks together to one block is possible.

* UMC 0.18μm mini@sic rules

When the standard block of 5mm x 5mm is divided into 9 regular square sub-blocks, customers participating in the mini@sic program can submit one sub-block or multiple sub-blocks, depending on the size of their design:

single sub-block: design may not be larger than 1525μm x 1525μm
2 sub-blocks: design may not be larger than 3240μm x 1525μm
3 sub-blocks: design may not be larger than 4960μm x 1525μm
4 sub-blocks: design may not be larger than 3240μm x 3240μm
6 sub-blocks: design may not be larger than 4960μm x 3240μm

Final price = number of sub-blocks needed to fit in the design * sub-block price.

UMS	Jan	Apr	May	Jul	Aug	Nov	Dec
UMS GH25\|GaN HEMT							11
UMS GH15\|GaN HEMT		24 *				27
UMS PH10\|GaAs pHEMT	30			31
UMS BES\|GaAs pHEMT					28
UMS ULRC-20\|GaAs			29

Important notes: Dates are GDS submission deadlines. Design registration must be done at least 4 weeks in advance.

(*) Run with BCB

Please fill in the Export Control questionnaire when registering your design and return it to silicon-asic@iis.fraunhofer.de UMS may postpone the run depends on the cummalative chip area. At the area less than 10 mm² the run will be started in consultation with UMS. Wafer size: 4″

UMS Pricelist	Standard EUR / mm²	Discount EUR / mm²
UMS GH15\|GaN HEMT ¹	3,600	3,240
UMS GH25\|GaN HEMT ¹	3,400	3,060
UMS PH10\|GaAs pHEMT ²	2,300	2,070
UMS BES\|GaAs ³	2,000	1,800
UMS ULRC\|GaAs⁴	1,600	1,440

Important notes:
¹Max. possible die area: 16 mm², available final X & Y dimension (mm): 1, 2, 3, 4, after fabrication and dicing.

Max. ratio X x Y dimension: 1:4. The customer Tape In area can be flexible and will be cut off according to the next possible manufactured chip size.

Die size includes 100 µm dicing street without inspection and test.

Delivery quantity: 16 dies in gel pack.

²Max. possible die area: 16 mm², available final X & Y sizes (mm): 1, 1.4, 2.4, 3.4, 4, after fabrication and dicing.

Max. ratio X x Y dimension: 1:3. The customer Tape In area can be flexible and will be cut off according to the next possible manufactured chip size.

Die size includes. 70 µm dicing street without inspection and test.

Delivery quantity 20 dies in gel pack.

³Max. possible die area: 16 mm², available final X & Y sizes (mm): 1, 1.4, 2.4, 3.4, 4, after fabrication and dicing.

Max. ratio X x Y dimension: 1:3. The customer Tape In area can be flexible and will be cut off according to the next possible manufactured chip size.

Die size includes. 70 µm dicing street without inspection and test.

Delivery quantity 20 dies in gel pack.

⁴Max. possible die area: 16 mm², available final X & Y sizes (mm): 1.4, 2, 2.4, 3.4, 4, after fabrication and dicing.

Max. ratio X x Y dimension: 1:4. The customer Tape In area can be flexible and will be cut off according to the next possible manufactured chip size.

Die size includes. 70 µm dicing street without inspection and test.

Delivery quantity 20 dies in gel pack.

Min fabrication cost equivalent to 4 mm² per customer.

X-FAB MPW	Jan	Feb	Mar	Apr	May	Jun	Jul	Aug	Sep	Oct	Nov	Dec
XT011 0.11µ HV SOI CMOS			18			17			2		25
XR013 0.13µ RF SOI CMOS *				21							10
XR013 0.13µ XIPD				21							10
XH018 0.18µ HV NVM CMOS E-FLASH	28			15			8			21
XP018 0.18µ NVM CMOS *		18				17			23
XT018 0.18µ HV SOI CMOS			25		13			12			25
XS018 0.18µ OPTO *			4				22
XH035 0.35µ HV CMOS			17					18			17
XG035 0.35µ GaN-on-Si				14			28					8
XMB10 MEMS									30

Important notes:

Dates are final gds deadlines. For a more detailed schedule please click on the “Detailed Submission Schedule” on top.

Registration should be done at least 4 weeks in advance.

* In case of cancellation, there is a possibility to order these technologies by MLM.

Please take a look at additional technology options:

X-FAB MPW Pricelist	Standard EUR / mm²	Discounted EUR / mm²
XT011 0.11µ HV SOI CMOS (MOS5, MOSLP, DTI, PSUB, METAL1, METAL2, METAL3, METAL4, METAL5, COPTHK, ALUCAP)	2,300	2,190
XR013 0.13μ CMOS XIPD (XIPD, METTHK1, METTHK2, METRB, PIMIDE, BUMP, METBQSL)	960	910
XR013 0.13μ RF SOI CMOS (METRB, METBQ)	2,325	2,210
XH018 0.18μ HV NVM CMOS E-FLASH (MET3, MET4, METMID, MET-THK)	2,025	1,925
XP018 0.18μ NVM CMOS (MET3, MET4, METMID, METTHK)	1,785	1,695
XT018 0.18μ HV SOI CMOS (MET3, MET4, METMID, METTHK)	2,040	1,940
XS018 0.18μ OPTO (MET3, MET4, MET5, METMID, MRPOLY, LVTN3D, BCH, MIMH, PPDB, 4TPIX, SFLATPV, ISOMOSA, MOS3LPPD)	1,495	1,420
XH035 0.35μ HV CMOS (MET4)	1,250	1,185
XMB10 MEMS	1,208 ¹	1,123 ¹

Important notes:

Price = area (mm²) * price/mm² with min. fabrication cost equivalent to 10mm².
Area will be rounded upwards to the next mm² (for instance, 12.24mm² will be charged as 13mm²).
Backgrinding (necessary for packaging) is not always possible and an additional cost might apply.

When four or more independent sub-designs are registered in one MPW submission to optimize the minimum charged area, an additional verification charge of 1,000 EUR will be applied.

Delivery of 50 dies is included. Purchasing additional dies is not always possible and an additional cost may apply.

¹ Delivery of 5 dies is included. Additional dies can be purchased for 10EUR/die (50 dies maximum).

X-FAB mini@sic		Jan	Feb	Mar	Apr	May	Jun	Jul	Aug	Sep	Oct	Nov	Dec
XH018 0.18µ HV NVM CMOS E-FLASH					6						12
XT018 0.18µ HV SOI CMOS						4						16

Important notes: Dates are final gds deadlines. For a more detailed schedule please click on the “Detailed Submission Schedule” on top.

Registration should be done at least 4 weeks in advance.

Please take a look at additional technology options:

X-FAB mini@sic Pricelist		Standard EUR / block	Discounted EUR / block
X-FAB XH018 0.18μ HV NVM CMOS E-FLASH (MET3, MET4, METMID, MET-THK)		5,700	5,300
X-FAB XT018 0.18μ HV SOI CMOS (MET3, MET4, METMID, METTHK)		5,800	5,400

Important notes:

Price = per block of 1520μm x 1520μm needed to fit the design in. Adding two blocks together to one block is possible.
Backgrinding (necessary for packaging) is not always possible and an additional cost might apply.

Delivery of 50 dies is included. Purchasing additional dies is not always possible and an additional cost may apply.

imec MPW	Apr	Jul	Oct
imec Si-Photonics Passives+		10
imec Si-Photonics iSiPP50G	17		16
imec GaN-IC on SOI 100V
GaN-IC on SOI 650V

Important notes: Dates are final gds deadlines. For a more detailed schedule please click on the “Detailed Submission Schedule” on top.

Admin. procedure must be finished at least 1 week before the dates indicated in the table.

imec MPW Pricelist Si-Photonics Passives+ ^{1, 2}	Standard EUR	Discounted EUR
Half block – horizontal (5.15mm x 2.5mm) or vertical (2.5mm x 5.15mm)	6,700	6,400
1 block (5.15mm x 5.15mm)	12,800	12,100
2 blocks – horizontal (10.45mm x 5.15mm) or vertical (5.15mm x 10.45mm)	22,700	21,500
4 blocks (10.45mm x 10.45mm)	44,000	42,000
Larger sizes	Please, contact epsiphot@imec.be
Extra Options
Extra set of half block chips (10 samples)	+2,500	+2,200
Extra set of chips (1 block or larger; 20 samples)	+2,500	+2,200
Si-Photonics iSiPP50G ^{1, 2}
Quarter block (2.5mm x 2.5mm)	11,000	10,500
Half block – horizontal (5.15mm x 2.5mm) or vertical (2.5mm x 5.15mm)	22,000	21,000
1 block (5.15mm x 5.15mm)	44,000	42,000
2 blocks – horizontal (10.45mm x 5.15mm) or vertical (5.15mm x 10.45mm)	88,000	83,500
4 blocks (10.45mm x 10.45mm)	165,000	157,000
Larger sizes	Please, contact epsiphot@imec.be
Extra Options
Extra set of quarter block chips (10 samples)	+2,500	+2,200
Extra set of half block chips (10 samples)	+2,500	+2,200
Extra set of chips (1 block or larger; 20 samples)	+2,500	+2,200

Important notes:

¹ There is a new process for the waveguides. Existing users, please be cautious.

² Number of prototypes in standard order depends on design size: 20 for 1 block or larger, 10 for half block or smaller.
Because of typical MPW logistics, we may sometimes deliver more chips than ordered.

imec MPW Pricelist GaN-IC on SOI 100V and 650V	Standard EUR	Discounted EUR
Half block (2.5mm x 5.18mm) *	22,000	20,240
Standard block (5.18mm x 5.18mm)	44,000	40,480
Double block (10.54mm x 5.18mm)	88,000	80,960
Extra Options
Extra set of chips (40 samples)	+5,000	+5,000
Sub-dicing **	+1,000	+1,000

Important notes: Regular number of samples is 40 .
Due to the nature of MPW logistics, more chips than ordered may sometimes be shipped.
* This option is only available to academic institutions.

** Per additional dicing lane, following MPW templates only. Sub-dicing options must be approved by the technical team. Please contact ganmpw@imec-int.com in advance to evaluate your request.

Pragmatic MPW		Jan	Feb	Mar	Apr	May	Jun	Jul	Aug	Sep	Oct	Nov	Dec
FlexIC Gen 3				12			17				26

Important notes:

Dates are final gds deadlines. For a more detailed schedule please click on the “Detailed Submission Schedule” on top.

Design registration should be done at least 4 weeks in advance.

Full-wafer runs are possible on demand. Please contact flexicmpw@imec-int.com.

Pragmatic MPW Pricelist	Standard EUR / mm²	Discounted EUR / mm²
FlexIC Gen 3 ^{1, 2}	900	800
Extra Options
Additional set of 10 dies ³	250	250

Important notes:

¹ Price = area (mm²) * price/mm². Delivery quantity = 50 dies in gel-box.

² Minimum die size is 3mm x 3mm. Larger die sizes and other dimensions are also possible, but please first contact flexicmpw@imec-int.com before registration.

³For more dies, please first contact flexicmpw@imec-int.com before registration.

For the full-wafer run pricelist, please contact flexicmpw@imec-int.com.

Science MPW	May	Jun	Sep	Oct	Dec
PolyMUMPs	27		21
SOIMUMPS	27		11		22
PiezoMUMPS		10		9

Important notes: Dates are final gds deadlines. For a more detailed schedule please click on the “Detailed Submission Schedule” on top.

Design registration must be done at least 4 weeks in advance.

Science MPW Pricelist		Standard EUR / block	Discounted EUR / block
PolyMUMPs (10mm x 10mm), SOIMUMPs (11 mm x 11mm), PiezoMUMPs (11mm x 11mm)		6,500	5000

SINTEF PiezoMEMS		Jan	Feb	Mar	Apr	May	Jun	Jul	Aug	Sep	Oct	Nov	Dec
SINTEF PiezoMEMS					8						7

Important notes:

Dates are final gds deadlines. For a more detailed schedule please click on the “Detailed Submission Schedule” on top.

SINTEF MPB Pricelist		Standard EUR	Discounted EUR
12 wafers		114,500	109,000
3 wafers		52,000	50,000

Important notes:

Additional services, such as dicing, are available on request.

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