SCHEDULES & PRICES

2024

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Schedules 2026

2026 RUN SCHEDULES AND PRICES

On this page you can find General MPW and mini@sic run schedules and prices for 2026.

If you need the 2025 schedules, please click here.

There are two prices in the EUROPRACTICE lists: Discounted and Standard.

DISCOUNTED PRICE

Three conditions should be met for Discounted prices:

Customer is an academic institution or a research facility from one of the 27 EU countries together with Albania, Armenia, Azerbaijan, Bosnia-Herzegovina, Georgia, Iceland, Israel, Liechtenstein, North Macedonia, Moldova, Montenegro, Norway, Switzerland, Turkey, Serbia, the UK and Ukraine.
Customer is a registered EUROPRACTICE member who has paid the Full-IC annual membership fee.
The intended design will be done for educational purposes or for publicly funded research.

STANDARD PRICE

Standard prices apply to all other customers.

To reserve your seat on a run, please register your design in the Registration Form or contact the EUROPRACTICE partner responsible for the technology.

STMicroelectronics MPW	Apr	May	Jun	Aug	Sep
ST BiCMOS55X	3			21
ST BiCMOS9MW		7
ST CMOS28FDSOI
ST HCMOS9A			5
ST P28					18

Important notes: Dates are GDS submission deadlines. Design registration has to be done at least 4 weeks in advance.

STMicroelectronics MPW Pricelist	Standard EUR / mm²	Additional area beyond X mm²	Discount EUR / project
ST BiCMOS55X	5,500	4,250²	1,200
ST BiCMOS9MW	3,500	2,950²	1,000
ST CMOS28FDSOI	9,000	6,750¹	1,500
ST HCMOS9A	3,550	3,150²	700
ST P28	12,150	9,100¹	1,500

Important notes:

All prices have a minimum charge of 1.25mm² including seal-ring.

Area = X*Y including seal-ring. The mentioned die size is referred to the Pre-Shrink die size.

Additional areas:

¹ Between 2 and 10 mm²

² Between 5 and 10 mm²

Reduced rate for additional mm² above 10mm²

TSMC MPW	Jan	Feb	Mar	Apr	May	Jun	Jul	Aug	Sep	Oct	Nov	Dec
TSMC 0.13µm CMOS BCD plus (12-inch)				1				5			4
TSMC 0.13µm CMOS Logic or MS/RF, GP or LP (12-inch)				1				5			4
TSMC 90nm CMOS Logic or MS/RF, GP or LP								5
TSMC 65nm CMOS Logic or MS/RF, GP or LP		25		8		3	8	26	3	7	4
TSMC 55nm CMOS Logic or MS/RF, GP or LP or ULP						3
TSMC 40nm CMOS Logic or MS/RF, LP (no triple gate oxide)		10	24	31		2	28		1 29		1
TSMC 40nm CMOS Logic or MS/RF, GP (no triple gate oxide)			31						1
TSMC 28nm CMOS Logic or RF HPC/HPC+	21	18		22	20		29	26	29	28	25
TSMC 22nm CMOS Logic or RF ULL		18		1 29		17	22	19		21	18
TSMC 16nm CMOS Logic or RF FinFET Compact	20		25		19		28		22		17
TSMC 7nm CMOS Logic or RF FinFET			25				*	*	*	*	*	*

Important notes:

Dates are GDS submission deadlines.

Several TSMC shuttles are extremely loaded. For any technology, please make your design registration as early as possible. We will work with you and do our best to get your design on the run. If required, a waiting list will be created.

* The schedule for the period July to December will be published on 16 March 2026.

Bumping is available upon request for all 12-inch technologies.

Contact eptsmc@imec.be if any of the following options are used: Bumping, MTP/OTP.

Prices for TSMC technologies can be calculated through the online Price Request Form:

Exceptionally, prices for the TSMC University FinFET Program can be found here:

When 4 or more independent sub-designs are registered in one MPW submission to optimise the minimum charged area, an additional verification charge of 1,000 USD is applicable. This is regardless of the request and charges for sub die sawing (6 USD per additional die obtained from the base MPW submission).

TSMC mini@sic	Jan	Feb	Mar	Apr	May	Jun	Jul	Aug	Sep	Oct	Nov	Dec
TSMC 0.13µm CMOS BCD plus			25							28
TSMC 65nm CMOS Low Power MS/RF		18		22		30		26		28		10 *
TSMC 65nm CMOS GP MS/RF			31						30
TSMC 40nm CMOS Low Power MS/RF			24						22
TSMC 28nm CMOS RF HPC+	14			15	13		22			21
TSMC 16nm CMOS RF FinFET Compact			18								10

Important notes:

Dates are GDS submission deadlines.

* Please note that this date is tentative and may be adjusted.

Please check additional technology options for TSMC mini@sic:

Please check additional technology options for the TSMC University FinFET Program:

TSMC mini@sic Pricelist	Standard prices		Discounted prices
	EUR / min area	EUR / extra area	EUR / min area	EUR / extra area
TSMC 130 BCD+ (min area = 6 mm²)	14,054	232 / 0.1 mm²	12,554	191 / 0.1 mm²
TSMC 65 LP/GP MS RF (min area = 1 mm²)	4,491	419 / 0.1 mm²	3,691	360 / 0.1 mm²
TSMC 40 LP MS RF (min area = 3 mm²) ¹	21,386	664 / 0.1 mm²	18,386	602 / 0.1 mm²
TSMC 28 HPC+ RF (min area = 1 mm²) ¹	10,609	919 / 0.1 mm²	8,509	834 / 0.1 mm²
TSMC 16 FFC RF (min area = 1mm²) ^{2, 3}	30,592	2,827 / 0.1 mm²	26,592	2,568 / 0.1 mm²

Important notes:

The prices are area based, and the aspect ratio is free to choose but it is strongly recommended not to have sides less than 1mm.
Subdicing is not supported on mini@sic.
Design registration must be done at least 3 months in advance, preferably at the moment of reservation.

¹ The areas in the table for 28nm and 40nm are on-silicon dimensions. This means the designed area can be (area/0.81).

²The areas in the table for 16nm indicates on-silicon dimensions. This means the designed area can be (area/0.9604).

Please check additional technology options for TSMC mini@sic:

³ Prices and technology options for the TSMC University FinFET Program can be found here:

UMC MPW	Jan	Feb	Mar	Apr	Jun	Jul	Aug	Sep	Oct	Nov
UMC 28N Logic/Mixed-Mode – HPC	19			20		20			19
UMC 40N Logic/Mixed-Mode – LP			30			27		21		30
UMC 65N Logic/Mixed-Mode/RF – LL				6		6		28
UMC L110AE Logic/Mixed-Mode/RF		9		27	29		31			23
UMC L180 Logic GII, Mixed-Mode/RF				6				28

Important notes: Dates are GDS submission deadlines. Design registration must be done at least 4 weeks in advance.

Additional technology options are available:

UMC MPW Pricelist	Standard EUR / block	Discounted EUR / block
UMC L180 Logic GII, Mixed-Mode/RF	19,000 ¹	18,060 ¹
UMC L110AE Logic/Mixed-Mode/RF	34,800 ¹	33,060¹
UMC L65nm Logic, Mixed-Mode/ RF – LL/SP	50,600 ²	48,080 ²
UMC 40N Logic/Mixed-Mode – LP	98,050 ²	93,160 ²
UMC 28N Logic/ Mixed-Mode – HPC	On request. Please, contact epumc@imec.be

Important notes:

¹ Price = per block of 5mm x 5mm needed to fit the design in.
² Price = per block of 4mm x 4mm needed to fit the design in.

When four or more independent sub-designs are registered in one MPW submission to optimize the minimum charged area, an additional verification charge of 1,000 EUR will be applied.

UMC mini@sic		Jan	Feb	Mar	Apr	May	Jun	Jul	Aug	Sep	Oct	Nov	Dec
UMC L180 Mixed-Mode/RF				30						21

Important notes: Dates are GDS submission deadlines. Design registration must be done at least 4 weeks in advance.

Additional technology options are available:

UMC mini@sic Pricelist		Standard EUR / block	Discounted EUR / block
UMC L180 Mixed-Mode/RF – 1P6M – 1.8V/3.3V *		4,110 ¹	3,430 ¹

Important notes:

¹ Price = per block of 1525μm x 1525μm needed to fit the design in. Adding two blocks together to one block is possible.

* UMC 0.18μm mini@sic rules

When the standard block of 5mm x 5mm is divided into 9 regular square sub-blocks, customers participating in the mini@sic program can submit one sub-block or multiple sub-blocks, depending on the size of their design:

single sub-block: design may not be larger than 1525μm x 1525μm
2 sub-blocks: design may not be larger than 3240μm x 1525μm
3 sub-blocks: design may not be larger than 4960μm x 1525μm
4 sub-blocks: design may not be larger than 3240μm x 3240μm
6 sub-blocks: design may not be larger than 4960μm x 3240μm

Final price = number of sub-blocks needed to fit in the design * sub-block price.

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2024

2026 RUN SCHEDULES AND PRICES

DISCOUNTED PRICE

STANDARD PRICE