SCHEDULES & PRICES

2026

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Schedules 2026

2026 RUN SCHEDULES AND PRICES

On this page you can find General MPW and mini@sic run schedules and prices for 2026.

If you need the 2025 schedules, please click here.

There are two prices in the Europractice lists: Discounted and Standard.

DISCOUNTED PRICE

Three conditions should be met for Discounted prices:

Customer is an academic institution or a research facility from one of the 27 EU countries together with Albania, Armenia, Azerbaijan, Bosnia-Herzegovina, Georgia, Iceland, Israel, Liechtenstein, North Macedonia, Moldova, Montenegro, Norway, Switzerland, Turkey, Serbia, the UK and Ukraine.
Customer is a registered Europractice member who has paid the Full-IC annual membership fee.
The intended design will be done for educational purposes or for publicly funded research.

STANDARD PRICE

Standard prices apply to all other customers.

To reserve your seat on a run, please register your design in the Registration Form or contact the Europractice partner responsible for the technology.

ams OSRAM MPW	Feb	Apr	May	Jul	Oct	Nov
ams OSRAM 0.18µ CMOS atC18C6SH 6M/1P/HR/MIM/TW (Triple-well), 1.8V/3.3V		13			19
ams OSRAM 0.18µ CMOS 6M/1P/HR/MIM/TW (Triple-well), 1.8V/5.0V					19
ams OSRAM 0.35µ CMOS C35B4C3 4M/2P/HR/5V IO	23			13		2
ams OSRAM 0.35µ CMOS C35OPTO 4M/2P/5V IO	23			13		2
ams OSRAM 0.35µ HV CMOS H35B4D3 120V 4M/2P/HP			11			23
ams OSRAM 0.35µ HV CMOS OPTO 4M/2P/HP			11			23
Passive Interposer (TSV, RDL, Bumping)						2

Important notes: Dates are GDS submission deadlines. Design Registration and Export Control must be done at least 2 weeks in advance. Please download and complete Export control and 21B file here.

Dates in red are tentative runs.

Fraunhofer IISB		Jan	Feb	Mar	Apr	May	Jun	Jul	Aug	Sep	Oct	Nov	Dec
4H-SiC CMOS HIGH TEMPERATURE					13

Important notes:

Dates are GDS submission deadlines. To participate in a process run, customers must have a valid NDA and register at least 4 weeks in advance. Please consult the latest PDK release for complete specifications and guidelines. For NDA, PDK download, and registration please contact silicon-asic@iis.fraunhofer.de .

Fraunhofer IISB Pricelist		Standard EUR / block	Discount EUR / block
4H-SiC CMOS HIGH TEMPERATURE (2.5mm x 5mm)¹		10,900	9,900
4H-SiC CMOS HIGH TEMPERATURE (5mm x 5mm)²		21,250	19,250

Important notes:
¹Max. design surface: 2.35mm x 4.85mm

²Max. design surface: 4.85mm x 4.85mm

Larger chip sizes and pricing are available on request.

GLOBALFOUNDRIES MPW	Jan	Feb	Mar	Apr	May	Jun	Jul	Aug	Sep	Oct	Dec
GLOBALFOUNDRIES SiGe 8XP			17					31
GLOBALFOUNDRIES 130nm BCDlite – Gen2		8						24
GLOBALFOUNDRIES 55 nm BCDlite			2			1		31
GLOBALFOUNDRIES 45RFE			10						14
GLOBALFOUNDRIES 45nm RFSOI		9					13
GLOBALFOUNDRIES 45nm SPCLO – Silicon Photonics				13				11			15
GLOBALFOUNDRIES 28 nm SLPe			2			1			7
GLOBALFOUNDRIES 22 nm FDSOI	27		16		4	30		17		5	5
GLOBALFOUNDRIES 12 nm LP+			26			25			10
GLOBALFOUNDRIES 180 MCU (open-source PDK)				26			19

Important notes: Dates are Registration deadlines after which designs cannot be accepted.

Final GDSII file must be submitted within 6 weeks after this date.

Dates in red are preliminary.

A cancellation fee is applicable if the registration is cancelled later than 2 weeks after the Registration deadline or if the customer is unable to provide a DRC-clean GDS before the Tapeout deadline.

GLOBALFOUNDRIES MPW Pricelist	Standard EUR / mm²	Discounted EUR / mm²
GLOBALFOUNDRIES SiGe 8XP	5,060 ¹	4,600 ¹
GLOBALFOUNDRIES 130 nm BCDlite	1,760 ¹	1,600 ¹
GLOBALFOUNDRIES 55 nm BCDlite	5,720 ²	5,200 ²
GLOBALFOUNDRIES 45RFE	10,230 ¹	9,300 ¹
GLOBALFOUNDRIES 45RFSOI	10,230 ¹	9,300 ¹
GLOBALFOUNDRIES 45nm SPCLO -Silicon Photonics (price per fixed block 5mm x 5mm)	242,000	220,000
GLOBALFOUNDRIES 28 nm SLPe	12,430 ³	11,300 ³
GLOBALFOUNDRIES 22 nm FDSOI	18,975 ³	17,250 ³
GLOBALFOUNDRIES 12 nm LP+	31,240 ³	28,400 ³
GLOBALFOUNDRIES 180 MCU (Open PDK)	913 ⁴	830 ⁴

Important notes:

¹ Price = area (mm²) * price/mm² with min. fabrication cost equivalent to 12 mm². Any edge length between 1.0 mm to 11 mm is possible. The mentioned die size is referred to the Pre-Shrink die size.

² Price = area (mm²) * price/mm² with min. fabrication cost equivalent to 9 mm². Any edge length between 1.0 mm to 11 mm is possible. The mentioned die size is referred to the Pre-Shrink die size.

³ Price = area (mm²) * price/mm² with min. fabrication cost equivalent to 4 mm². The mentioned die size is referred to the Pre-Shrink die size.

⁴ Price = area (mm²) * price/mm² with min. fabrication cost equivalent to 6 mm². The mentioned die size is referred to the Pre-Shrink die size.

GLOBALFOUNDRIES MPW	Jan	Feb	Mar	Apr	May	Jun	Jul	Aug	Sep	Oct	Dec
GLOBALFOUNDRIES SiGe 8XP			17					31
GLOBALFOUNDRIES 130nm BCDlite – Gen2		8						24
GLOBALFOUNDRIES 55 nm BCDlite			2			1		31
GLOBALFOUNDRIES 45RFE			10						14
GLOBALFOUNDRIES 45nm RFSOI		9					13
GLOBALFOUNDRIES 45nm SPCLO – Silicon Photonics				13				11			15
GLOBALFOUNDRIES 28 nm SLPe			2			1			7
GLOBALFOUNDRIES 22 nm FDSOI	27		16		4	30		17		5	5
GLOBALFOUNDRIES 12 nm LP+			26			25			10
GLOBALFOUNDRIES 180 MCU (open-source PDK)				26			19

Important notes: Dates are Registration deadlines after which designs cannot be accepted.

Final GDSII file must be submitted within 6 weeks after this date.

Dates in red are preliminary.

GLOBALFOUNDRIES mini@sic Pricelist	Standard EUR / mm²	Discounted EUR / mm²
GLOBALFOUNDRIES SiGe 8XP	7,260 ¹	6,600 ¹
GLOBALFOUNDRIES 130nm BCDlite – Gen2	3,080 ²	2,800 ²
GLOBALFOUNDRIES 55 nm BCDlite	8,250 ¹	7,500 ¹
GLOBALFOUNDRIES 45RFE	13,200 ¹	12,000 ¹
GLOBALFOUNDRIES 45RFSOI	13,200 ¹	12,000 ¹
GLOBALFOUNDRIES 45nm SPCLO -Silicon Photonics	154,000 ⁴	140,000 ⁴
GLOBALFOUNDRIES 28 nm SLPe	18,370 ³	16,700 ³
GLOBALFOUNDRIES 22 nm FDSOI	25,080 ³	22,800 ³
GLOBALFOUNDRIES 12 nm LP+	38,500 ³	35,000 ³

Important notes:

¹ Price = area (mm²) * price/mm² with min. fabrication cost equivalent to 2.5 mm². The mentioned die size is referred to the Pre-Shrink die size.

² Price = area (mm²) * price/mm² with min. fabrication cost equivalent to 5 mm². The mentioned die size is referred to the Pre-Shrink die size.

³ Price = area (mm²) * price/mm² with min. fabrication cost equivalent to 1 mm².The mentioned die size is referred to the Pre-Shrink die size.

⁴ Price = fixed block size of 5mm x 2.455mm or 2.455mm x 5mm.

IHP MPW	Jan	Feb	Mar	May	Jul	Sep	Oct	Nov
IHP SG13S SiGe:C Bipolar/Analog, Ft/Fmax= 250/340GHz, 7M/MIM, optional with TSV				1	31			6
IHP SG13SCu FEOL process SG13S together with 8 layer Cu BEOL from X-FAB containing 4 thin & 2 thick Cu layers, a thin Al layer and Al top layer.					31			6
IHP SG13CMOS SiGe:C includes all features of SG13G2 but not HBT, CMOS 7M/MIM, PDK von SG13G2				1	31			6
IHP SG13G2 SiGe:C Bipolar/Analog, Ft/Fmax= 350/450GHz, 7M/MIM, optional with TSV				1	31			6
IHP SG13G2Cu FEOL process SG13G2 together with 8 layer Cu BEOL from X-FAB containing 4 thin & 2 thick Cu layers, a thin Al layer and Al top layer.		13			31			6
IHP SG13G3 FEOL, the same FEOL process SG13G3Cu, with Al-BEOL option for research and prototyping purpose only					31			6
IHP SG13G3Cu SiGe:C Bipolar/Analog, Ft/Fmax= 470/650GHz FEOL process with 8 layer Cu BEOL from X-FAB containing 4 thin & 2 thick Cu layers, a thin Al layer and Al top layer		13			31			6
IHP BEOL SG13 (M1 and Metal Layers Above), optional TSV				15				6
IHP INTM4TM2 Interposer technology, 2 thin and 2 thick Al-BEOL layer on a HRes substrate, MIM capacitor, Thin film Res.			16		27
IHP MEMRES (RRAM) for SG13G2				1				6
SG25H7_EPIC A monolithic photonic BiCMOS technology combining CMOS, high-performance npn HBTs (fT / fmax = >350/>500 GHz), and full photonic device set for C/O-band., 7M/MIM,Ge Photo-diode							2
IHP SG25H7_PIC Incl. additional photonic design layers along with BiCMOS BEOL layers on SOI wafers.	16
Open Source SG13G2						7

Important notes:

Dates are Registration and Export Control information deadlines. Please download the Export Control file here.

Final GDSII file must be submitted within 10 calendar days after this date.

Final chip area incl. Sealring_complete must be provided 7 calendar days after the regsitration

The final chip area may not deviate by more than 5% from the registered area including the sealring.

Chip thickness different from 300µm or 200µm require extra fee.

MEMRES is available for IHP SG13S technology with extra charge.

TSV is available for IHP SG13S and SG13G2 technologies with extra charge.

Cu Pillar and Bumping are available for all IHP technologies with extra charge; SG13C on request.

Local Backside Etching (LBE) is not offered for EPIC runs and runs with Cu-BEOL.

* For research and prototyping purposes only.

IHP MPW Pricelist	Standard EUR / mm²	Discounted EUR / mm²
IHP SG13S SiGe:C Bipolar/Analog, Ft/Fmax= 250/340GHz, 7M/MIM	6,300 ¹	5,355 ¹
IHP SG13SCu FEOL process SG13S together with 8 layer Cu BEOL from X-FAB containing 4 thin & 2 thick Cu layers, a thin Al layer and Al top layer.	6,300 ¹	5,355¹
IHP SG13CMOS SiGe:C includes all features of SG13G2 but not HBT, CMOS 7M/MIM, PDK von SG13G2	4,500 ¹	3,825 ¹
IHP SG13CMOS5L SiGe:C A CMOS technology offered for open-source education designs, includes FEOL SG13CMOS, but noisolated NMOS, 4 thin metal layer and one 2μm thick TopMetal and no MIM capacitor
IHP SG13G2 SiGe:C Bipolar/Analog, Ft/Fmax= 350/450GHz, 7M/MIM	7,300¹	6,205 ¹
IHP SG13G2Cu FEOL process SG13G2 together with 8 layer Cu BEOL from X-FAB containing 4 thin & 2 thick Cu layers, a thin Al layer and Al top layer.	7,300 ¹	6,205 ¹
IHP SG13G3 FEOL, the same FEOL process SG13G3Cu, with Al-BEOL option for research and prototyping purpose only	9,000 ¹	7,650 ¹
IHP SG13G3Cu SiGe:C Bipolar/Analog, Ft/Fmax= 470/650GHz FEOL process with 8 layer Cu BEOL from X-FAB containing 4 thin & 2 thick Cu layers, a thin Al layer and Al top layer	9,000 ¹	7,650 ^1,3
IHP SG25H7_PIC Incl. additional photonic design layers along with BiCMOS BEOL layers on SOI wafers.	4,500 ^1,3	3,825 ^1,3
IHP BEOL SG13 (M1 and Metal Layers Above)	1,300 ¹	1170 ¹
IHP INTM4TM2 Interposer technology, 2 thin and 2 thick Al-BEOL layer on a HRes substrate, MIM capacitor, Thin film Res.	900	765
SG25H7_EPIC A monolithic photonic BiCMOS technology combining CMOS, high-performance npn HBTs (fT / fmax = >350/>500 GHz), and full photonic device set for C/O-band., 7M/MIM,Ge Photo-diode	9000^1,3	7650^1,3
IHP Special Services
Bumping (available for all IHP technologies), SG13C on request	on request²	on request²
Localized Back side Etching (available for IHP technologies with AL BEOL only), not offered for EPIC/PIC runs	5,000²	4,250 ²
TSV to ground (SG13S / G2)	12,500 ^2,3	10,625 ^2,3
Cu Pillar	on request²	on request²
MEMRES Module, CMOS integrated memristive module based on resistive TiN / HfO2-x / TiN switching devices, on time fee offered for SG13G2	2,500²	2,000²
MEMRES Module additional fee per mm²	600¹	510¹

Important notes:

¹ Price = area (mm²) * price/mm² with min. fabrication cost equivalent to 0.8mm².
The chip area is inclusive of the filler cells outside the seal ring.
² One-off fee
³ Delivery quantity: 25 dies.

Fabrication of a chip area less than 0.8mm² and X & Y ratio larger than 1:3 is on request.

* For research and prototyping purposes only.

Standard MPW price is meant for designs of industrial customers.

Discounted MPW price is meant for designs created for educational purposes or publicly funded research for non-EU countries.

IHP mini@sic	Jan	Feb	Mar	May	Jul	Sep	Oct	Nov
IHP SG13S SiGe:C Bipolar/Analog, Ft/Fmax= 250/340GHz, 7M/MIM, optional with TSV				1	31			6
IHP SG13SCu FEOL process SG13S together with 8 layer Cu BEOL from X-FAB containing 4 thin & 2 thick Cu layers, a thin Al layer and Al top layer.					31			6
IHP SG13CMOS SiGe:C includes all features of SG13G2 but not HBT, CMOS 7M/MIM, PDK von SG13G2				1	31			6
IHP SG13G2 SiGe:C Bipolar/Analog, Ft/Fmax= 350/450GHz, 7M/MIM, optional with TSV				1	31			6
IHP SG13G2Cu FEOL process SG13G2 together with 8 layer Cu BEOL from X-FAB containing 4 thin & 2 thick Cu layers, a thin Al layer and Al top layer.		13			31			6
IHP SG13G3 FEOL, the same FEOL process SG13G3Cu, with Al-BEOL option for research and prototyping purpose only					31			6
IHP SG13G3Cu SiGe:C Bipolar/Analog, Ft/Fmax= 470/650GHz FEOL process with 8 layer Cu BEOL from X-FAB containing 4 thin & 2 thick Cu layers, a thin Al layer and Al top layer		13			31			6
IHP BEOL SG13 (M1 and Metal Layers Above), optional TSV				15				6
IHP INTM4TM2 Interposer technology, 2 thin and 2 thick Al-BEOL layer on a HRes substrate, MIM capacitor, Thin film Res.			16		27
IHP MEMRES (RRAM) for SG13G2				1				6
SG25H7_EPIC A monolithic photonic BiCMOS technology combining CMOS, high-performance npn HBTs (fT / fmax = >350/>500 GHz), and full photonic device set for C/O-band., 7M/MIM,Ge Photo-diode							2
IHP SG25H7_PIC Incl. additional photonic design layers along with BiCMOS BEOL layers on SOI wafers.	16
Open Source SG13G2						7