Technology characteristics | CMOS technology substrate resistivity is in the range of 9-18 ohm-cm
Core Voltages: 0.9V, 1V, IO Voltages: 1.5V, 1.8V
1.12 nm thin gate oxide for 0.9 V
2.5 nm thick gate oxide for 1.5 V and 1.8 V
Mini. lithographic image of 40 nm (gate only)
Operating junction temperature: -40°C to 125°C
One BEOL STACK options: 9LM Metallization stack
Seven levels of all-copper global metal
1x, 2x, and 8x thick wires at relaxed pitches
Low-K and TEOS/FTEOS Inter Level Dielectrics
Planarized passivation and interlevel dielectrics
High-value resistor 1.5K Ohms/square
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| C-band (1550 nm) coherent transceivers modules
O-band (1310 nm) direct detect transceivers
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| Polarization splitter & rotator, modulators, detectors
Phase shifter, connection options (Polymer bundle or Fiber Butt)
Vertical grating incoupler: iograt
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| Regular Vt, floating-body FETs
Ultrahigh Vt, floating-body FETs
Analog, body-contacted FETs
Thick-oxide, body-contacted FETs
Precision resistors,Thick-oxide decoupling capacitor
Efuse, Ge EPI Photo diode, Nitride wave guide in MOL
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| Fab8 – Malta, New York, USA
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| 50 dies for general MPW and 50 dies for mini@sic run
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| Cadence, Synopsys, Siemens EDA
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| 25mm² with fix dimensions of 5mm x 5mm
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| Supported
Block size: 5mm x 2.455mm or 2.455mm x 5mm (Pre-Shrink die size)
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