TSMC

Technologies

ACCESS TO BACKEND VIEWS

From now on, customers can also get access to the backend views of standard cell libraries, as long as there is a firm tape out plan. To request the access, please complete this form.

Your request will be reviewed by TSMC. We would like to warn you that the review procedure can take up to 3 months due to high number of applications.

DETAILS

0.13µm Low Power BCD Plus is a 12 inch, automotive qualified, technology targeted towards highly integrated mobile PMIC applications. It’s based on 0.13µm Low Power MS to which it adds HV MOSFET and BJT devices up to 36V, and offers up to 3 gate voltage options (1.5/3.3/5V).

0.13µm CMOS High Voltage, Low Power, BCD Plus
Technology characteristics
Shrink technology: NO
Core voltage: 1.5V
I/O voltage: 5V (dual gate voltage) or 3.3V/5V (triple gate voltage)
HV transistors (Vds): 10/12/16/20/24/28/36V
STI
Wells: Retrograde well CMOS technology on <100> P- substrate wafer.
Six LV wells, three HV wells and N+ Buried Layer (NBL)
Substrate resistivity 8~12 ohm.cm on <100> P- substrate
Standard Vt, Low Vt, Native Vt
Temperature range: -40C to 150C
# of metals: 4 or 6 (copper metals) + 1 (optional) aluminium redistribution layer *
Interconnect material: Copper (first 6 metal layers)
Interconnect dielectric: FSG (FluoroSilicate Glass)
Top metal: 8KA only **
CMP on STI, contact, via and inter-metal dielectric layers
MoM
MiM density: 1fF/µm2 or 1.5fF/µm2, mutual exclusive
Passivation: single (default; no aluminium RDL) or dual (optional; when aluminum RDL is required)
OTP (from TSMC & 3rd party) / MTP (only 3rd party)
Wafer size
12 inch
Deliverables
# of dies (no wafer!): 100 dies / wafer
Design tools
PDK: Cadence CDBA and OA
Simulation tools
Hspice, Spectre
Verification tools DRC
Cadence (PVS), Siemens EDA (Calibre), Synopsys (ICV)
Verification tools LVS
Cadence, Siemens EDA, Synopsys
Parasitic extraction tools
Cadence, Siemens EDA, Synopsys
P&R tools
Cadence, Siemens EDA, Synopsys
Foundry IP
Standard cell libraries available from 3rd party IP providers (ARM, Dolphin, …)
1.5V/3.3V, hybrid linear slim I/O library that contains both standard and analog slim I/O
SRAM compilers available from 3rd parties
eFuse (from TSMC; paying option)
MPW block size
Min. 25 mm2, flexible aspect ratio
Mini@sic characteristics
Supported
Min area: 6mm2

* More options may become available at a later stage. TSMC can process 3 to 6 metals and UTM is possible, but no PDK installation currently supports these options.

** 33KA UTM may become available at a later stage. TSMC can process UTM, and UTM is mentioned as an option in the DRM, but no PDK installation currently supports this option.

For applications in consumer electronics, computers, mobile computing, automotive electronics, IoT, and smart wearables.

0.13µm CMOS Logic or MS/RF, General Purpose
Technology characteristics
Shrink technology: NO
Core voltage: 1.2V
I/O voltage: 2.5 or 3.3V
Shallow Trench Isolation (STI)
Wells: Retrograde twin well cmos technology on <100> P-substrate. Substrate resistivity 8-12ohm-cm
Tripple Well, Deep N-well (optional)
Vt options: lvt, svt, hvt,uhvt, native
Temperature range: -40C to 125C
# of metals: 3 to 8 +ALRDL
Interconnect dielectric: FSG
Top metal: 8KA
CMP on STI, contact, via and inter-metal dielectric layers
MoM
Varactors
MS/RF options
MIM capacitor for MS & RF process: 1fF/µm2
High-Q copper inductor
Top metal: UTM, 33.5K
Single passivation, Dual passivation optional
Wafer size
12 inch
Deliverables
# of dies (no wafer!): 40-dies (8″), 100 dies (12″) / wafer
Design tools
PDK: Cadence CDBA and OA, Mentor
Simulation tools
HSPICE, Eldo, Spectre
Verification tools DRC
Cadence, Siemens EDA
Verification tools LVS
Cadence, Siemens EDA
Parasitic extraction tools
Cadence, Siemens EDA
P&R tools
Cadence, Siemens EDA, Synopsys
Foundry IP
9-track core cell library, with 5V I/O devices, SVt
1.2/3.3V regular,linear universal standard I/O
1.2V/2.5V & 1.2/3.3V Universal Analog I/O compatible with Linear Universal Standard I/O
1.2V/2.5V & 1.2/3.3V , hybrid linear slim I/O library that contains both standard and analog slim I/O
5V tolerant, linear universal standard I/O
1.2V/3.3V, 5V tolerant, staggered universal standard I/O
SRAM compilers from 3rd party
MPW block size
Min. 25 mm2, flexible aspect ratio
Mini@sic characteristics
Not supported

For applications in consumer electronics, computers, mobile computing, automotive electronics, IoT, and smart wearables.

0.13µm CMOS Logic or MS/RF, Low Power
Technology characteristics
Shrink technology: NO
Core voltage: 1.5V
I/O voltage: 2.5 or 3.3V
Shallow Trench Isolation (STI)
Wells: Retrograde twin well cmos technology on <100> P-substrate. Substrate resistivity 8-12ohm-cm
Tripple Well, Deep N-well (optional)
Vt options: lvt, svt, native
Temperature range: -40C to 125C
# of metals: 3 to 8 (CU) (+ALRDL)
Interconnect dielectric: FSG
Top metal: 8KA
CMP on STI, contact, via and inter-metal dielectric layers
MoM
Varactors
MS/RF options
MIM capacitor for MS & RF process: 1fF/µm2
High-Q copper inductor
Top metal: UTM, 33.5K
Single passivation, Dual passivation optional
Wafer size
12 inch
Deliverables
# of dies (no wafer!): 40-dies (8″), 100 dies (12″) / wafer
Design tools
PDK: Cadence CDBA and OA, Mentor
Simulation tools
HSPICE, Eldo, Spectre
Verification tools DRC
Cadence, Siemens EDA
Verification tools LVS
Cadence, Siemens EDA
Parasitic extraction tools
Cadence, Siemens EDA
P&R tools
Cadence, Siemens EDA, Synopsys
Foundry IP
9-track core cell library
MPW block size
Min. 25 mm2, flexible aspect ratio
Mini@sic characteristics
Not supported

This is a general-purpose product for applications with a 1.0V core design and with 1.8, 2.5 or 3.3V capable IO’s for digital consumer, Networking , HDD and FPGA.

90nm CMOS Logic or MS/RF, General Purpose
Technology characteristics
Shrink technology: NO
Core voltage: 1.0V
I/O voltage: 1.8, 2.5 or 3.3V
Shallow Trench Isolation (STI)
Wells: Retrograde twin well cmos technology on P-substrate
Tripple Well, Deep N-well (optional)
Multiple Vt options (lvt, svt, hvt, native)
Dual gate oxide and tripple gate oxide process
Temperature range: -40C to 125C
# of metals: 3 to 9 (+ALRDL)
Interconnect material: Cu + AlCu pad
LK inter-metal dielectric for thin metal
Top metal: 5.6 KA, 8.5KA
CMP on STI, contact, via and inter-metal dielectric layers
MoM
MS/RF options
MIM capacitor for MS & RF process: 1.0, 1.5, 2.0 fF/µm2(mutually exclusive)
High-Q copper inductor
Top metal: UTM, 34KA
Varactors
Dual passivation
Options that need special attention
Fuse RAM
Wafer size
12 inch
Deliverables
# of dies (no wafer!): 100 dies / wafer (12″)
Design tools
PDK: Cadence CDBA, Cadence OA, Mentor, iPDK
Simulation tools
Hspice, Eldo, Spectre
Verification tools DRC
Cadence, Siemens EDA
Verification tools LVS
Cadence, Siemens EDA
Parasitic extraction tools
Cadence, Siemens EDA
P&R tools
Cadence, Siemens EDA, Synopsys
Foundry IP
7,9,14-track core cell library, multi-Vt
1.0V/2.5V &1.0V/3.3V hybrid staggered slim I/O library that contains both standard and analog slim I/O
1.0V/2.5V &1.0V/3.3V linear staggered slim I/O library that contains both standard and analog slim I/O
1.0v/2.5v, 3.3v tolerant, staggered universal standard I/O
1.0V/3.3V, 5V Tolerant, Staggered Universal Standard I/O
SRAM compilers from 3rd party
MPW block size
16 mm2, flexible aspect ratio
Mini@sic characteristics
Not supported

This is a general-purpose product for applications with a 1.2V core design and with 2.5 or 3.3V capable IO’s for mobile applications, such as Cellular, WLAN, BT.

90nm CMOS Logic or MS/RF, Low Power
Technology characteristics
Shrink technology: NO
Core voltage: 1.2V
I/O voltage: 2.5 or 3.3V
Shallow Trench Isolation (STI)
Wells: Retrograde twin well cmos technology on P-substrate
Tripple Well, Deep N-well (optional)
Multiple Vt options (ulvt, lvt, svt, hvt, native)
Dual gate oxide and tripple gate oxide process
Temperature range: -40C to 125C
# of metals: 3 to 9 (CU) (+ALRDL)
Interconnect material: Cu + AlCu pad
LK inter-metal dielectric for thin metal
Top metal: 5.6 KA, 8.5KA
CMP on STI, contact, via and inter-metal dielectric layers
MoM
Varactors
MS/RF options
MIM capacitor for MS & RF process: 1.0, 1.5, 2.0 fF/µm2(mutually exclusive)
Ultra Low Vt
High-Q copper inductor
Top metal: UTM, 34KA
Dual passivation
Options that need special attention
Fuse RAM
Wafer size
12 inch
Deliverables
# of dies (no wafer!): 100 dies / wafer (12″)
Design tools
PDK: Cadence CDBA and OA
Simulation tools
Hspice, Eldo, Spectre
Verification tools DRC
Cadence, Siemens EDA
Verification tools LVS
Cadence, Siemens EDA
Parasitic extraction tools
Cadence, Siemens EDA
P&R tools
Cadence, Siemens EDA, Synopsys
Foundry IP
7,9,14-track core cell library, multi-Vt
1.2v/2.5v &1.2V/3.3V Universal Analog I/O compatible with Linear Universal Standard I/O
1.2V/2.5V & 1.2V/3.3V Regular, Linear Universal Standard I/O
1.2V/3.3V, regular, linear standard slim I/O
1.2V/3.3V, hybrid staggered slim I/O library that contains both standard and analog slim I/O
SRAM compilers from 3rd party
MPW block size
16 mm2, flexible aspect ratio
Mini@sic characteristics
Not supported

It is a popular and well supported node.

65nm CMOS Logic or MS/RF, General purpose
Technology characteristics
Shrink technology: NO
Core voltage: 1.0V
I/O voltage: 2.5V (1.8V underdrive, 3.3V overdrive)
Shallow Trench Isolation (STI)
Wells: Retrograde twin well for low well sheet resistance and better latch-up behavior.
Optional Deep N-Well
<100> P- substrate wafer. Substrate resistivity 8-12ohm-cm
Dual Gate Oxide (1 for core, 1 for IO)
Vt options: lvt, svt, hvt, native
Temperature range: -40C to 125C
# of metals: 3 to 9 Cu + alrdl
Interconnect dielectric: LK
Top metal: 5KA, 9KA, 12.5KA, 34KA
CMP on STI, contact, metals, vias and passivation
MoM
MiM density: 1fF/µm2, 1.5fF/µm2 or 2fF/µm2, mutually exclusive
Passivation: dual layers
Options that need special attention
OTP/MTP
SRAM Cell
Wafer size
12 inch
Deliverables
# of dies (no wafer!): 100 dies / wafer
Design tools
PDK: Cadence CDBA and OA, TSMC iPDK, Mentor
Simulation tools
HSPICE, Eldo, Spectre
Verification tools DRC
Cadence, Siemens EDA, Synopsys, Magma, TSMC iDRC
Verification tools LVS
Cadence, Siemens EDA, Synopsys, Magma
Parasitic extraction tools
Cadence, Siemens EDA, Synopsys
P&R tools
Cadence, Siemens EDA, Synopsys
Foundry IP
12-track / 10-track / 9-track core cell libraries, multi-vt, coarse grain
1.0V/2.5V staggered (fail-safe digital, 5V input tolerant digital, hybrid small footprint digital/analog and regular analog) I/O library
SRAM compilers from 3rd party
MPW block size
12 mm2
Mini@sic characteristics
Supported
Min area: 1mm2
mini@sic Technology options

It is a popular and well supported node.

65nm CMOS Logic or MS/RF, Low Power
Technology characteristics
Shrink technology: NO
Core voltage: 1.2V
I/O voltage: 2.5V (1.8V underdrive, 3.3V overdrive)
Shallow Trench Isolation (STI)
Wells: Retrograde twin well for low well sheet resistance and better latch-up behavior.
Optional Deep N-Well
<100> P- substrate wafer. Substrate resistivity 8-12ohm-cm
Dual Gate Oxide (1 for core, 1 for IO)
Vt options: lvt, svt, hvt, mLowvt, native
Temperature range: -40C to 125C
# of metals: 3 to 9 Cu + alrdl
Interconnect dielectric: LK
Top metal: 5KA, 9KA, 12.5KA, 34KA
CMP on STI, contact, metals, vias and passivation
MoM
MiM density: 1fF/µm2, 1.5fF/µm2 or 2fF/µm2, mutually exclusive
Passivation: dual layers
Options that need special attention
OTP/MTP
SRAM Cell
Wafer size
12 inch
Deliverables
# of dies (no wafer!): 100 dies / wafer
Design tools
PDK: Cadence CDBA and OA, TSMC iPDK, Mentor
Simulation tools
HSPICE, Eldo, Spectre
Verification tools DRC
Cadence, Siemens EDA, Synopsys, Magma, TSMC iDRC
Verification tools LVS
Cadence, Siemens EDA, Synopsys, Magma
Parasitic extraction tools
Cadence, Siemens EDA, Synopsys
P&R tools
Cadence, Siemens EDA, Synopsys
Foundry IP
12-track / 10-track / 9-track / 7-track core cell libraries, multi-vt, coarse grain
1.2V/2.5V staggered (fail-safe digital, 5V input tolerant digital, hybrid small footprint digital/analog and regular analog) I/O library
1.2V/2.5V linear (digital, hybrid small footprint digital/analog and regular analog) I/O library
SRAM compilers
MPW block size
12 mm2
Mini@sic characteristics
Supported
Min area: 1mm2
mini@sic Technology options

Well supported advanced node, 40G = 45GS.

40nm CMOS Logic or MS/RF, General Purpose
Technology characteristics
Shrink technology: YES
Core voltage: 0.9V
I/O voltage: 2.5V (1.8V underdrive, 3.3V overdrive) or true 1.8V
Shallow Trench Isolation (STI)
Wells: Retrograde twin well for low well sheet resistance and better latch-up behavior.
Optional Deep N-Well
<110> P- substrate wafer. Substrate resistivity 8-12ohm-cm
Dual Gate Oxide (1 for core, 1 for IO)
Vt options: lvt, svt, hvt, native
Temperature range: -40C to 125C
# of metals: 3 to 10 Cu + alrdl
Interconnect dielectric: ELK
Top metal: 3.1KA, 9KA, 12.5KA, 34KA
CMP on STI, contact, metals, vias and passivation
MoM
Passivation: dual layers
Options that need special attention
OTP/MTP
SRAM Cell
Wafer size
12 inch
Deliverables
# of dies (no wafer!): 100 dies / wafer
Design tools
PDK: Cadence CDBA and OA, TSMC iPDK
Simulation tools
HSPICE, Eldo, Spectre
Verification tools DRC
Cadence, Siemens EDA, Synopsys, Magma, TSMC iDRC
Verification tools LVS
Cadence, Siemens EDA, Synopsys, Magma, TSMC iLVS
Parasitic extraction tools
Cadence, Siemens EDA, Synopsys
P&R tools
Cadence, Siemens EDA, Synopsys
Foundry IP
12-track / 9-track core cell libraries, multi-vt, coarse grain
0.9V/1.8V staggered (fail-safe digital, 5V input tolerant digital and regular analog) I/O library
0.9V/2.5V staggered (fail-safe digital, 5V input tolerant digital and regular analog) I/O library
SRAM compilers
MPW block size
9 mm2
Mini@sic characteristics
Not supported

It is a well supported advanced node.

40nm CMOS Logic or MS/RF, Low Power
Technology characteristics
Shrink technology: YES (90% linear shrink)
Core voltage: 1.1V
I/O voltage: 2.5V (1.8V underdrive, 3.3V overdrive)
Shallow Trench Isolation (STI)
Wells: Retrograde twin well for low well sheet resistance and better latch-up behavior.
Optional Deep N-Well
<110> P- substrate wafer. Substrate resistivity 8-12ohm-cm
Dual Gate Oxide (1 for core, 1 for IO)
Vt options: lvt, svt, hvt, native
Temperature range: -40C to 125C
# of metals: 3 to 10 Cu + alrdl
Interconnect dielectric: ELK
Top metal: 3.1KA, 9KA, 12.5KA, 34KA
CMP on STI, contact, metals, vias and passivation
MoM
Passivation: dual layers
Options that need special attention
OTP/MTP
SRAM Cell
Wafer size
12 inch
Deliverables
# of dies (no wafer!): 100 dies / wafer
Design tools
PDK: Cadence CDBA and OA, TSMC iPDK, Mentor
Simulation tools
HSPICE, Eldo, Spectre
Verification tools DRC
Cadence, Siemens EDA, Synopsys, Magma, TSMC iDRC
Verification tools LVS
Cadence, Siemens EDA, Synopsys, Magma, TSMC iLVS
Parasitic extraction tools
Cadence, Siemens EDA, Synopsys
P&R tools
Cadence, Siemens EDA, Synopsys
Foundry IP
12-track / 9-track core cell libraries, multi-vt, coarse grain
1.1V/2.5V staggered (fail-safe digital, 5V input tolerant digital, hybrid small footprint digital/analog and regular analog) I/O library
SRAM compilers
MPW block size
9 mm2
Mini@sic characteristics
Supported
Min area: 3mm2 (post-shrink)
mini@sic Technology options

The TSMC 28nm technology is the most performant planar mainstream solution that evolved through the years due to constant enhancements in the manufacturing process. It supports a wide range of applications, including CPUs, GPUs, high-speed networking chips, smart phones, APs, tablets, home entertainment, consumer electronics, automotive and IoT.

 

The 28nm RF (28HPC+ RF) technology also provides support for 110GHz mmWave and for 5G mmWave RF.

28nm CMOS HPC+ Logic, RF
Technology characteristics
Shrink technology: YES
Core voltage: 0.9V
I/O voltage:
– MPW (1.8V or 2.5V),
– mini@sic (1.8V only)
Shallow Trench Isolation (STI)
Wells: Retrograde twin well for low well sheet resistance and better latch-up behavior.
Triple well, Deep N-Well in option
Dual Gate Oxide
Vt options (only 4 out of 7): ulvt, lvt, hvt, uhvt, ehvt, sram, sram_ull
1.8V I/O based 5V HVMOS: Not offered for RF HPC+ flavor
HighRes resistors
Temperature range: -40C to 125C
# of metals: 5 to 10 Cu + ALRDL
Interconnect dielectric: ELK
Top metal: Up to 35kA (please check with eptsmc@imec.be first)
CMP on STI, contact, via and passivation
MoM capacitor
Passivation: dual layers
Options that need special attention
SRAM Cell (GL, ULL)
Vt’s: maximum of 4 VT types in one design.
Wafer size
12 inch
Deliverables
100 dies, no wafer
Design tools
PDK: TSMC iPDK
Simulation tools
HSPICE, Eldo, Spectre
Verification tools DRC
Cadence, Siemens EDA, Synopsys
Verification tools LVS
Cadence, Siemens EDA, Synopsys
Parasitic extraction tools
Cadence, Siemens EDA, Synopsys
P&R tools
Cadence, Siemens EDA, Synopsys
Foundry IP
12-track / 9-track / 7-track core cell libraries, multi-vt’s
0.9V/1.8V hybrid staggered (fail-safe digital and regular analog) I/O library
SRAM compilers by TSMC , ARM, Synopsys
MPW block size
6mm² (on silicon)
Mini@sic characteristics
Supported
Min area: 1mm2 (post-shrink)
mini@sic Technology options

The TSMC 28nm technology is the most performant planar mainstream solution that evolved through the years due to constant enhancements in the manufacturing process. It supports a wide range of applications, including CPUs, GPUs, high-speed networking chips, smart phones, APs, tablets, home entertainment, consumer electronics, automotive and IoT.

28nm CMOS HPC Logic, RF
Technology characteristics
Shrink technology: YES
Core voltage: 0.9V
I/O voltage: MPW (1.8V or 2.5V)
Shallow Trench Isolation (STI)
Wells: Retrograde twin well for low well sheet resistance and better latch-up behavior.
Triple well, Deep N-Well in option
Dual Gate Oxide
Vt options (only 4 out of 7): ulvt, lvt, hvt, uhvt, ehvt, sram, sram_ull
1.8V I/O based 5V HVMOS
HighRes resistors
Temperature range: -40C to 125C
# of metals: 5 to 10 Cu + ALRDL
Interconnect dielectric: ELK
Top metal: Up to 35kA (please check with eptsmc@imec.be first)
CMP on STI, contact, via and passivation
MoM capacitor
Passivation: dual layers
Options that need special attention
SRAM Cell (GL, LL)
Vt’s: maximum of 4 VT types in one design.
Wafer size
12 inch
Deliverables
100 dies, no wafer
Design tools
PDK: TSMC iPDK
Simulation tools
HSPICE, Eldo, Spectre
Verification tools DRC
Cadence, Siemens EDA, Synopsys
Verification tools LVS
Cadence, Siemens EDA, Synopsys
Parasitic extraction tools
Cadence, Siemens EDA, Synopsys
P&R tools
Cadence, Siemens EDA, Synopsys
Foundry IP
12-track / 9-track / 7-track core cell libraries, multi-vt’s
0.9V/1.8V hybrid staggered (fail-safe digital and regular analog) I/O library
SRAM compilers by TSMC , ARM, Synopsys
MPW block size
6mm² (on silicon)
Mini@sic characteristics
Not supported

TSMC’s 22nm technology is developed based on its 28nm process. EUROPRACTICE supports the Ultra Low Leakage flavor of the process: 22ULL. The technology is TSMC’s most advanced planar node. Compared to the 28nm high-performance compact (28HPC) technology, it provides a 10% area reduction with more than 10% speed gain or 20% power reduction. It is suitable for applications including mobile devices, automotive electronics, IoT and consumer products. Additionally, TSMC’s 22nm ULL RF technology adds key mmWave mobile communication devices.

22nm CMOS ULP and ULL
Technology characteristics
Shrink technology: YES (85.5% linear shrink from 32nm)
Core voltage: 0.8V
I/O voltage: 1.8V or 2.5V
Shallow Trench Isolation (STI)
Wells: Retrograde twin well for low well sheet resistance and better latch-up behavior
Triple well, Deep N-Well in option
Dual Gate Oxide
Vt options:
– ULP: UHVt, HVt, SVt, LVt, ULVt, Native
– ULL: UHVt, HVt, SVt, LVt, ULVt, EHVt, Native
SRAM:
– ULP: GL SRAM
– ULL: GL SRAM, ULL SRAM, ELL SRAM
High-R and unsilicided OD resistors
NW resistors: NW resistor within OD and NW resistor under STI
Temperature range: -40C to 125C junction temperature
# of metals: 3 to 10 Cu + AlRDL
Top metal: Up to 35KA (please check with eptsmc@imec.be)
HVMOS:
– I/O 1.8V based HVMOS in ULL/ULP
– I/O 2.5V based HVMOS in ULL only
CMP on STI, contact, metals, vias, passivation
Wafer size
12 inch
Deliverables
100 dies, no wafer
Design tools
PDK: TSMC iPDK
Verification tools DRC
Cadence, Siemens EDA, Synopsys
Verification tools LVS
Cadence, Siemens EDA, Synopsys
Parasitic extraction tools
Cadence, Siemens EDA, Synopsys
P&R tools
Cadence, Synopsys
I/O
0.8V/1.8V or 0.8V/2.5V.
2.5V overdrive to 3.3V
2.5V underdrive to 1.8V
1.8V underdrive to 1.5V
1.8V underdrive to 1.2V
SRAM
ULP: SRAM compilers by TSMC
ULL: SRAM compilers by ARM
MPW block size
6 mm² (on silicon)
Mini@sic characteristics
Not supported

EUROPRACTICE offers a flagship technology TSMC 16nm CMOS logic or RF FinFET Compact 0.8V/1.8V. It provides superior performance and power consumption advantage for next generation high-end mobile computing, network communication, consumer and automotive electronic applications.

16nm CMOS logic FinFET Compact
Technology characteristics
Shrink technology: 2% shrink
Core voltage: 0.8V
I/O voltage: 1.8V
Shallow Trench Isolation (STI)
Triple well, Deep N-Well in option
Dual gate oxide
Vt options: hvt, svt, lvt, ulvt, low noise vt
5V HVMOS
TiN High Resistor
N+/P+ metal gate allows symmetrical design of NMOS and PMOS devices
Temperature range: -40C to 125C
# of metals: 6 to 13 Cu plus last metal level in Al pad
Interconnect dielectric: ELK
HD MiM capacitors
Passivation: dual layers
Wafer size
12 inch
Deliverables
100 dies, no wafer
Design tools
PDK: TSMC iPDK
Simulation tools
HSPICE, Eldo, Spectre
Verification tools DRC
Cadence, Siemens EDA, Synopsys
Verification tools LVS
Cadence, Siemens EDA, Synopsys
Parasitic extraction tools
Cadence, Siemens EDA, Synopsys
P&R tools
Cadence, Siemens EDA, Synopsys
Foundry IP
9-track, 7.5-track body biased core cell libraries with gate lengths of 16, 20 and 24nm
0.8V/1.8V hybrid staggered I/O library
SRAM compilers by TSMC, ARM_Artisan, ARM ltd, GUC, Synopsys
MPW block size
4 mm²
Mini@sic characteristics
Supported for RF
Min area: 1mm2 (post-shrink)
mini@sic Technology options

TSMC 7nm FinFET offers industry-leading power and performance for a broad array of applications, ranging from high-to-mid end mobile,
consumer applications, AI, networking, 5G infrastructure, GPU, and high-performance computing.

 

Since it is classified as a leading node technology, access to it is subject to review and approval by TSMC.

7nm CMOS logic FinFET Compact
Technology characteristics
Shrink technology: NO
Core voltage: 0.75V
I/O voltage: 1.8V
Shallow Trench Isolation (STI)
Triple well, Deep N-Well in option
Dual gate oxide
Vt options: svt, lvt, ulvt
NW, TiN High Resistor
N+/P+ metal gate allows symmetrical design of NMOS and PMOS devices
Temperature range: -40C to 125C
# of metals: 9 to 15 Cu plus last metal level in Al pad
Interconnect dielectric: ELK
MOM capacitors
HD MiM capacitors for decoupling
Passivation: dual layers
Wafer size
12 inch
Deliverables
100 dies, no wafer
Design tools
PDK: TSMC iPDK
Simulation tools
HSPICE, Eldo, Spectre
Verification tools DRC
Cadence, Siemens EDA, Synopsys
Verification tools LVS
Cadence, Siemens EDA, Synopsys
Parasitic extraction tools
Cadence, Siemens EDA, Synopsys
P&R tools
Cadence, Siemens EDA, Synopsys
Foundry IP
Cell height 240nm or 300nm, body biased PODE core cell libraries with gate lengths of 8 and 11nm
0.75V/1.8V, general purpose I/O library in combination with solder bump or Cu-pillar (no wirebond)
SRAM compilers
MPW block size
2 mm²
Mini@sic characteristics
Not supported

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