Graphene is an atomically thin material with extraordinary properties enabling next-generation devices and technologies. Its seamless integration with platforms such as CMOS BEOL enables enhanced functionality and efficient incorporation into existing semiconductor processes, paving the way for new innovations.
VTT uses commercially available Si CMOS readout wafers and standard semiconductor manufacturing techniques to produce CMOS integrated graphene-based devices at the wafer scale. The process flow enables graphene-based devices such as Field Effect transistors, resistors, and capacitors connected to the Si CMOS readout circuitry. VTT’s fabrication and quality control processes monitor key parameters in the runs, ensuring the customer’s devices are up to the targeted parameters. An example of the graphene FET CMOS integration by VTT is discussed in this publication.
The offered baseline process for is a CMOS integrated GFET including via, back gate, bottom contact, graphene and encapsulation modules. The design of the device can be adjusted within the specifications listed below.
Process Step | Layer | Material |
|---|---|---|
0 | METMID / PAD | |
1
| CMOS Via | |
2 | Via metallization | TiW/Au |
3 | Local Back Gate | Ti/Au |
4 | Gate Dielectric | ALD Al2O3 + HfO |
5 a | Bottom contact | Ti/Au |
5 b | Liquid gate | Ti/Pt |
6 | Graphene | Monolayer CVD graphene |
7 | Encapsulation | ALD Al2O3 + HfO |
Parameter | Criteria | Value |
|---|---|---|
Graphene Mobility | Mobility at gm_max | >1000 cm²/Vs |
Avg. Sheet Resistance | Doping = -1*1013 cm-2 CNP | ~1 kΩ ~4 kΩ |
Avg. Contact Resistance | Doping = -1*1013 cm-2 | ~1 kΩ µm |
Device yield | RDSmax < 1 MΩ On/off > 5 Ig_max < 10 nA | >75 % |
Avg. Dirac point: | Doping | ~ -4*1012 cm-2 |
Safe gate-source voltage range | Ig_max < 10 nA | ± 10 V |
