Imec offers EUROPRACTICE customers access to the UMC technologies.
UMC L180 MM/RF 1.8V/3.3V 1P6M technology.
L180 Mixed Mode/RF 1.8V/3.3V 1P6M | |
|---|---|
Technology characteristics | Shrink technology: NO Core voltage: 1.8V I/O voltage: 3.eV Shallow Trench Isolation (STI) Triple well Substrate resistivity: 15~25 Ohm.cm on <100> P- substrate Std Vt, 3.3V LVt PMOS, 3.3V LVt NMOS, 1.8V LVt PMOS, 1.8V LVt NMOS, 3.3V zero_Vt NMOS Temperature range: -40C to 125C # of metals: 6 Interconnect material: Al Dielectric: FSG Top metal: 8KA, 12 KA or 20KA Inductors MoM MiM: 1fF/µm2 Passivation: single |
Options that need special attention | OTP |
Wafer size | 8 inch
|
Deliverables | # of dies: 50 for an MPW, 25 for a mini@sic run |
Design tools | Cadence CDBA, Cadence OA, Laker, Mentor, Tanner, ADS |
Simulation tools | HSPICE, Eldo, Spectre
|
Verification tools DRC | Cadence, Siemens EDA, Synopsys |
Verification tools LVS
| Cadence, Siemens EDA, Synopsys |
Parasitic extraction tools
| Cadence, Siemens EDA, Synopsys |
P&R tools
| Cadence, Synopsys
|
Foundry IP
| Faraday standard cell libraries Faraday I/O library 3.3V Faraday memories |
MPW block size
| 5mm x 5mm |
Mini@sic characteristics
| Supported Block size: 1525µm x 1525µm I/O voltage: 3.3V Metal stack: 1P6M with 20KA top metal Mimcap density 1fF/µm2 |
Bumping | On request |
0.11 µm Logic and Mixed-Mode 1P8M Metal Metal Capacitor Al Advanced Enhancement Process.
L110AE Logic/Mixed-Mode/RF | |
|---|---|
Technology characteristics | Shrink technology: YES Core voltage: 1.2V I/O voltage: 1.8V/2.5V/3.3V/5V Shallow Trench Isolation (STI) Triple well Substrate resistivity 15~25 ohm.cm on <100> P- substrate Vt options: HS, SP, LL, HS_SP, HS_LL, SP_LL and HS_SP_LL Temperature range: -40C~125C # of metals: 8 Interconnect material: AlCu Dielectric: USG Top metal: 20KA or 40KA Inductors MoM MiM: 1.0fF/µm2 or 1.5fF/µm2 or 2.0fF/µm2 Passivation: single |
Wafer size | 8 inch |
Deliverables | # of dies (no wafer!): 50 on an MPW, 25 on a mini@sic |
Design tools | Cadence CDBA, Laker |
Simulation tools | HSPICE, Eldo, Spectre
|
Verification tools DRC | Cadence, Siemens EDA, Synopsys |
Verification tools LVS
| Cadence, Siemens EDA, Synopsys |
Parasitic extraction tools
| Cadence, Siemens EDA, Synopsys |
P&R tools
| Cadence, Synopsys
|
Foundry IP
| Gate density I/O voltage, OD, UD RAM/ROM/Dual port/register files) |
MPW block size
| 5mm x 5mm |
Mini@sic characteristics
| Not supported |
Bumping | At request |
65 nm Logic and Mixed-Mode Low Leakage Low-K Process.
L65N Logic/Mixed-Mode/RF – Low Leakage | |
|---|---|
Technology characteristics | Shrink technology: NO Core voltage1.2V I/O voltage 1.8V, 2.5V, 3.3V overdrive MOAT Twin and triple well Substrate resistivity 7~17 ohm.cm on Epi- substrate LL_RVT, LL_HVT, LL_LVT Temperature range -40C to 125C # of metals: 10 Interconnect material: Cu Interconnect dielectric: FSG Top metal: 8kA, 32.5kA RDL: 32.5kA Inductors MoM MiM: 2fF/µm2 Passivation: single |
Wafer size | 12 inch |
Deliverables | 90 samples |
Design tools | Cadence CDBA, Laker |
Simulation tools | HSPICE, Eldo, Spectre
|
Verification tools DRC | Cadence, Siemens EDA, Synopsys |
Verification tools LVS
| Cadence, Siemens EDA, Synopsys |
Parasitic extraction tools
| Cadence, Siemens EDA, Synopsys |
P&R tools
| Cadence, Synopsys
|
Foundry IP
| Standard cells I/O library: NA |
MPW block size
| 4000µm x 4000µm |
Mini@sic characteristics
| Supported Block size: 1875µm x 1875µm 2.5V/2.5_OD3.3V 1P8M1T0F1U (U=32.5kA) Mimcap 2fF |
Bumping | At request |
40 nm Logic and Mixed-Mode Low Power Process.
40N Logic/Mixed-Mode – Low Power | |
|---|---|
Technology characteristics | Shrink technology: NO Core voltage 0.9V I/O voltage 1.8V, 2.5V MOAT Twin and triple well Substrate resistivity 10~15 ohm.cm on Epi- substrate LP_RVT, LP_HVT, LP_LVT, LP_UHVT Temperature range -40C to 125C # of metals: 10 Interconnect material: Cu Interconnect dielectric: FSG Top metal: 8kA, 12kA, 32.5kA RDL: 12.5kA, 34kA MoM MiM: 2fF/µm2 Passivation: single |
Wafer size | 12 inch |
Deliverables | 90 samples |
Design tools | Cadence CDBA, Laker |
Simulation tools | HSPICE, Eldo, Spectre
|
Verification tools DRC | Cadence, Siemens EDA, Synopsys |
Verification tools LVS
| Cadence, Siemens EDA, Synopsys |
Parasitic extraction tools
| Cadence, Siemens EDA, Synopsys |
P&R tools
| Cadence, Synopsys
|
Foundry IP
| Standard cells I/O library: NA |
MPW block size
| 4000µm x 4000µm |
MPW Turnaround time | 18-20 weeks |
Mini@sic characteristics
| Not supported |
Bumping | At request |
28 nm Logic and Mixed-Mode High Performance Compact Process.
28N Logic/ Mixed-Mode – HPC | |
|---|---|
Technology characteristics | Shrink technology: NO Core voltage 1.0, 1.1V I/O voltage 1.8V, 2.5V MOAT Twin and triple well Substrate resistivity 15~25 ohm.cm on Epi- substrate UHVT, HVT, RVT, LVT, ULVT Temperature range -40C to 125C # of metals: 10 Interconnect material: Cu Dielectric: FSG Top metal: 8kA, 12kA, 32.5kA RDL: 14.5kA, 28kA MoM MiM: 2fF/µm2 Passivation: single |
Wafer size | 12 inch |
Deliverables | 90 samples |
Design tools | Cadence CDBA, Laker |
Simulation tools | HSPICE, Eldo, Spectre
|
Verification tools DRC | Cadence, Siemens EDA, Synopsys |
Verification tools LVS
| Cadence, Siemens EDA, Synopsys |
Parasitic extraction tools
| Cadence, Siemens EDA, Synopsys |
P&R tools
| Cadence, Synopsys
|
Foundry IP
| Standard cells I/O library: NA |
Dummy filling | by Foundry |
MPW block size
| 4000µm x 4000µm |
MPW Turnaround time | 20-22 weeks |
Mini@sic characteristics
| Not supported |
Bumping | At request |
Explore more UMC technology options for General MPW and mini@sic runs:
